37.2.4.4.1 Transmit Buffer and FIFO Operation

The I3CxTXB register is safe to write when the contents of the register is empty. This condition is represented through the Transmit Buffer Empty TXBE bit. This also results in the I3CxTXIF system level interrupt flag being set, which can also be used as a DMA trigger.

When the user software writes data to the I3CxTXB register, the TXBE and I3CxTXIF bits are cleared. The data are then passed onto the Transmit FIFO, which sets the Transmit FIFO Not Empty TXFNE bit and, subsequently, the TXBE/I3CxTXIF bits as well. If the data are written to the I3CxTXB Transmit Buffer faster than the Controller’s reading speed, it is possible that the Transmit Buffer and FIFO will eventually become full and the TXBE and I3CxTXIF bits will remain cleared, signifying that the I3CxTXB register cannot accept new data. If the I3CxTXB Transmit Buffer is written to when it is full (TXBE = 0), a Transmit Buffer Write Error occurs and the TXWEIF interrupt flag is set. The TXBE and I3CxTXIF flags are set again as soon as the Controller reads from the Transmit FIFO and the data in the I3CxTXB register are shifted into the Transmit FIFO. The TXFNE bit is cleared after all the data in the Transmit FIFO have been transmitted on the bus or a buffer reset operation has been performed using the CLRTXB bit. It is also possible that the Controller attempts to read from the Target when the Transmit FIFO is empty (TXFNE = 0), in which case a Transmit Underrun occurs, the TXUIF interrupt flag is set, and the read request is NACKed by the Target.

Table 37-8. Summary of Transmit Status and Interrupt Flags
I3CxTXB Transmit Buffer Status	Transmit FIFO Status	TXBE/I3CxTXIF	TXFNE	Other Interrupts
Empty	Empty	`1`	`0`	TXUIF is set when read is requested by the Controller⁽¹⁾
Full	Empty	`0`	`0`	TXUIF is set when read is requested by the Controller⁽¹⁾ TXWEIF is set when write is attempted to the I3CxTXB register
Empty	Partially Full or Full	`1`	`1`
Full	Partially Full or Full	`0`	`1`	TXWEIF is set when write is attempted to the I3CxTXB register
Note: The TXUIF Transmit Underrun interrupt flag is set alongside the ACK/NACK bit of the address header after the R/W bit has been transmitted. If a read is requested by the Controller and the data are not available in the Transmit FIFO, the Target module NACKs the read request and sets the TXUIF flag simultaneously.

Important:

While the Target will typically continue to transmit data (with End-of-Data T-bit = 1) during a Private Read or IBI transaction as long the Transmit FIFO is not empty (TXFNE = 1), the transmit operation can be limited if the Maximum Read Length (I3CxMRL register) or IBI Payload Size Limit (I3CxIBIPSZ register) is set. When the Maximum Read Length or the IBI Payload Size Limit has been reached in the appropriate transaction, the Target will stop transmitting further data (with End-of-Data T-bit = 0) even if the Transmit FIFO is not empty. This does not affect the operation of other Transmit Status and Interrupt flags.
This Target module will always NACK an I²C/Private Read request when the Transmit FIFO is empty (TXFNE = 0). When data are available in the Transmit FIFO (TXFNE = 1), the Target module will ACK an I²C/Private Read request when the ACKP bit = 0. To NACK an I²C/Private Read request when data are in the Transmit FIFO, the ACKP bit must be set to 1. With ACKP bit set, a one-time ACK can be performed using the ACKPOS bit. Refer to Private Read Transaction for more information.