37.2.7.2.9 Target Reset Action (RSTACT)

The Controller uses the Broadcast and Direct Write RSTACT CCC to configure the next Target Reset action. The RSTACT CCC is used in conjunction with the Target Reset Pattern. Figure 37-32 shows the frame format for Broadcast Write RSTACT CCC, whereas Figure 37-33 shows the frame format for Direct Write RSTACT CCC.

The Controller uses the Direct Read RSTACT CCC to retrieve the Target’s most recently configured Reset action or the Target’s Reset recovery timing. Refer to Table 37-14 for more information on the data returned by the Target. Figure 37-34 shows the frame format for Direct Read RSTACT CCC.

The RSTACT CCC uses a Defining Byte. The different values of the defining byte and their corresponding action are listed in Table 37-14.

Table 37-14. RSTACT Defining Byte Values
Defining Byte Value Description Direct or Broadcast Write Action Direct Read Action
0x00 No Reset on Target Reset Pattern Target ACKs and the user software configures the necessary reset action(1); Refer to Target Reset for details Target ACKs and returns the currently set Defining Byte value from I3CxRSTACT register(1)
0x01 Reset I3C Peripheral Only (Default)
0x02 Reset the Whole Target
0x03 Debug Network Adaptor Reset(2) Target NACKs Target NACKs
0x04 Virtual Target Detect(2) Target NACKs Target NACKs
0x05 to 0x3F Reserved by MIPI – –
0x40 to 0x7F Reserved for vendors and external standards – –
0x80 Reserved by MIPI – –
0x81 Return Time to Reset Peripheral – Target ACKs and returns 0xFF (Controller should assume maximum time of 1 ms)
0x82 Return Time to Reset Whole Target – Target ACKs and returns 0xFF (Controller should assume maximum time of 1s)
0x83 Return Time for Debug Network Adaptor Reset(2) – Target NACKs
0x84 Return Virtual Target Indication(2) – Target NACKs
0x85 to 0xBF Reserved for timing for MIPI reserved values – Target ACKs and returns 0xFF
0xC0 to 0xFF Reserved for timing for vendors and external standards reserved values – Target ACKs and returns 0xFF
Note:
  1. Any Reset action (or inaction) configured via the RSTACT CCC is stored in the I3CxRSTACT register. It is recommended for the user to read this value and perform the appropriate reset action in the software. Refer to the Target Reset section for more information. The I3CxRSTACT register continues to hold the value of the most recent RSTACT CCC defining byte value until it is overwritten by the next RSTACT CCC defining byte or the register is reset due to a reset action. The user can also reset the register manually by writing 0xFF to it.
  2. This Target module does not support MIPI Debug or Virtual Target capability, hence defining bytes 0x03, 0x04, 0x83 and 0x84 are not supported. The hardware functions are undefined for these defining bytes.
  3. All defining bytes received during a Direct or Broadcast RSTACT CCC are stored in the I3CxRSTACT register regardless of whether they are supported or not.
Figure 37-32. Broadcast Write RSTACT Frame Format
Figure 37-33. Direct Write RSTACT Frame Format
Figure 37-34. Direct Read RSTACT Frame Format