37.4.41 I3CxRSTACT
Note:
- The Controller may update the value of this field by issuing a RSTACT CCC.
- The value of this register is
retained until the next RSTACT CCC is received. It is recommended for the
user to reset this register in software to
0xFFfor a proper detection of the Target Reset Pattern. Refer to Target Reset for details. - In case of a race condition, user writes always take precedence over hardware events.
| Name: | I3CxRSTACT |
| Address: | 0x0B1, 0x0E4 |
RSTACT Defining Byte
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| RSTACT[7:0] | |||||||||
| Access | R/W/HS/HC | R/W/HS/HC | R/W/HS/HC | R/W/HS/HC | R/W/HS/HC | R/W/HS/HC | R/W/HS/HC | R/W/HS/HC | |
| Reset | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | |
Bits 7:0 – RSTACT[7:0] RSTACT CCC Defining Byte
The value of this field is the Defining Byte of the most recent RSTACT CCC.