2.6.2 Importing Other Constraint Files

The JTAG clock constraint and the asynchronous clocks constraint must be imported. These constraints (.sdc) files are available in the DesignFiles_directory\HW\src\constraints folder.

To import and map the constraint files, perform the following steps:

1. On the Timing tab, click Import.
2. Navigate to the DesignFiles_directory\HW\src\constraints, and select the timing_user_constraints.sdc file.
3. Select the Synthesis, Place and Route, and Timing Verification checkboxes next to the timing_user_constraints.sdc file.

   This constraint file defines that the PF_CCC_C0_0 output clock and PF_DDR3_C0_0 AXI clock are asynchronous clocks.

4. Click Save.