2.4 Connecting IP Instances in SmartDesign

Connect the IP blocks in SmartDesign using any of the following methods:

• Using the Smart Search and Connect icon: You can initiate the connection mode in SmartDesign by clicking the Smart Search and Connect icon in the SmartDesign toolbar, as shown in the following figure. You can search and select multiple ports and connect or disconnect them at once.

  

• Using the Connect option in the Context menu: You can also connect pins by selecting the pins, and then selecting Connect from the context menu. To connect multiple pins, hold down the Ctrl key while selecting the pins. Right-click the input source signal, and select Connect. To disconnect signals, right-click the input source signal, and select Disconnect.
• You can select the source pin, click and drag the wire to the destination pin until you see a ‘+’ sign. The pins will be automatically connected after you release the button of the mouse.
• Right-clicking on a pin provides a list of options like Mark Unused, Edit Slice, Tie Low, Promote to Top-Level, and Tie High. Use these options for individual pins settings.

The following figure shows the Mi-V subsystem in SmartDesign with all IP blocks connected and top-level I/Os.

To connect the IP blocks, perform the following steps:

1. Set the pins as follows on INIT_MONITOR_0:
   1. Select PCIE_INIT_DONE, USRAM_INIT_DONE, SRAM_INIT_DONE, XCVR_INIT_DONE, USRAM_INIT_FROM_SNVM_DONE, USRAM_INIT_FROM_UPROM_DONE, USRAM_INIT_FROM_SPI_DONE, SRAM_INIT_FROM_SNVM_DONE, SRAM_INIT_FROM_UPROM_DONE, SRAM_INIT_FROM_SPI_DONE, and AUTOCALIB_DONE pins.
   2. Right-click the pins, and select Mark Unused.
   3. Connect the FABRIC_POR_N pin to FPGA_POR_N pin of CORERESET_PF_C0_0 and CORERESET_PF_C1_0.
   4. Connect the DEVICE_INIT_DONE pin to CORERESET_PF_C0_0:INIT_DONE.
   5. Connect the BANK_1_CALIB_STATUS pin to CORERESET_PF_C1_0:INIT_DONE.
   6. Connect the BANK_6_VDDI_STATUS pin to CORERESET_PF_C0_0:BANK_x_VDDI_STATUS, CORERESET_PF_C0_0:BANK_y_VDDI_STATUS, CORERESET_PF_C1_0:BANK_x_VDDI_STATUS, and CORERESET_PF_C1_0:BANK_y_VDDI_STATUS.
2. Set the pins as follows on PF_CCC_C0_0:
   • Right-click the REF_CLK_0 pin, and select Promote to Top Level.
   • Connect the other pins as specified in the following table.

   Table 2-1. PF_CCC_C0_0 Pin Connections

   Connect From	Connect To
   PLL_LOCK_0	CORERESET_PF_C0_0: PLL_LOCK and CORERESET_PF_C1_0: PLL_LOCK
   OUT0_FABCLK_0	CORERESET_PF_C0_0: CLK and CORERESET_PF_C1_0:CLK
   	MIV_RV32_C0_0: CLK
   	PF_DDR3_C0_0: PLL_REF_CLK
   	MIV_ESS_C1_0: PCLK
   	COREAXI4INTERCONNECT_C0_0: ACLK
   PLL_POWERDOWN_N_0	CORERESET_PF_C0_0: PLL_POWERDOWN_B

3. Set the pins of CORERESET_PF_C0_0 as follows:
   • Connect EXT_RST_N pin to PF_DDR3_C0_0:CTRLR_READY.
   • Right-click SS_BUSY and FF_US_RESTORE pins and tie them low.
4. Connect the CORERESET_PF_C0_0: FABRIC_RESET_N to the following pins.
   • MIV_RV32_C0_0: RESETN
   • COREAXI4INTERCONNECT_C0_0: ARESETN
   • MIV_ESS_C1_0: PRESETN
   Important: As PF_DDR3_C0_0:CTRL_READY pin is connected to CORERESET_PF_C0_0:EXT_RST_N, the Mi-V processor is held in reset until the DDR3 controller is ready. The rest of the system is out of reset as soon as device initialization is done.
5. Set the pins of CORERESET_PF_C1_0 as follows:
   • Right-click SS_BUSY and FF_US_RESTORE pins and tie them low using the Tie Low option.
   • Select the EXT_RST_N pin and promote it to top level and rename it to resetn.
   • Connect the FABRIC_RESET_N pin to PF_DDR3_C0_0: SYS_RESET_N.
   • Right-click the PLL_POWERDOWN_B pin and mark it unused.
6. Set the pins as follows on COREJTAGDEBUG_C0_0:
   • Expand JTAG HEADER.
   • Right-click the TDI, TCK, TMS, and TRSTB pins, and select Promote to Top Level.
   • Expand JTAG HEADER.
   • Right-click the TDO pin, and select Promote to Top Level.
   • Connect the other pins as specified in the following table.

   Table 2-2. DEBUG_TARGET Pin Connections

   Connect From	Connect to
   COREJTAGDEBUG_C0_0:TGT_TCK_0	MIV_RV32_C0_0:JTAG_TCK
   COREJTAGDEBUG_C0_0:TGT_TRSTN_0	MIV_RV32_C0_0:JTAG_TRSTN
   COREJTAGDEBUG_C0_0:TGT_TMS_0	MIV_RV32_C0_0:JTAG_TMS
   COREJTAGDEBUG_C0_0:TGT_TDI_0	MIV_RV32_C0_0:JTAG_TDI
   COREJTAGDEBUG_C0_0:TGT_TDO_0	MIV_RV32_C0_0:JTAG_TDO

7. Set the pins as follows on MIV_RV32_C0_0:
   • Right-click EXT_RESETN pin, and select Mark Unused.
   • Right-click on TIME_COUNT_IN[63:0] and tie it low.
   • Connect the APB_INITIATOR to MIV_ESS_C1_0: APB_0_mINITIATOR.
   • Connect the AXI4_INITIATOR to COREAXI4INTERCONNECT_C0_0: AXI4mmaster0.
8. Connect the COREAXI4INTERCONNECT_C0_0 pins as specified in the following table.

   Table 2-3. COREAXI4INTERCONNECT_C0_0 Pin Connections

   COREAXI4INTERCONNECT_C0_0 Pin Name	Connect To
   S_CLK0	PF_DDR3_C0_0:SYS_CLK
   AXI4mslave0	PF_DDR3_C0_0:AXI4slave0

9. Set the pins as follows on PF_DDR3_C0_0:
   • Right-click the PLL_LOCK output pin, and select Mark Unused.
   • Right-click the CTRLR_READY pin, and select Promote to Top Level for debug purpose. The CTRLR_READY signal is used to monitor the status of the DDR controller.
   • Ensure that the other pins are promoted to top level.
10. Set the pins as follows on MIV_ESS_C1_0:
    • Select UART_RX and SPI_SDI.
    • Right-click, and select Promote to Top Level.
    • Select UART_TX, SPI_SCK, SPI_SDO, SPI_SS, and GPIO_OUT[3:0].
    • Right-click, and select Promote to Top Level.
    • Right-click the SPI_IRQ, GPIO_INT[3:0], and select Mark Unused.
    • Select GPIO_IN[3:0] and select Tie low.
    • Right-click on the port "UART_TX", and rename it to "TX".
    • Similarly, rename "UART_RX" to "RX", "SPI_SCK" to "SPISCLKO", "SPI_SDO" to "SPISDO", and "SPI_SDI" to "SPISDI".
11. Right-click the top SmartDesign canvas, and select Auto Arrange Layout.
12. Click File > Save top.

The IP blocks are successfully connected.