7 Revision History

• Updated the document for Libero® v2024.2.
• Updated the .job filepath and TCL script filepath throughout the document.
• Updated Figure 2-10 and Figure 2-11 in the Instantiating DDR3 Memory Controller section.
• Updated Figure 5-1 in the Appendix 2 - DDR3 Configuration section.

• Updated the document for Libero v2024.1
• Updated Figure 2-4 in Instantiating Mi-V Processor IP section
• Updated Figure 2-9 in Instantiating AXI Interconnect Bus IP section
• Updated "DDR3_0" to "PF_DDR3_C0" in Instantiating DDR3 Memory Controller section
• Updated "DDR3_0_0" to "PF_DDR3_C0_0" and "CCC_0" to "PF_CCC_0" in Instantiating PolarFire Clock Conditioning Circuitry (CCC) section
• Updated Figure 2-15 in Instantiating PolarFire Initialization Monitor section
• Updated "reset_syn_0" to "corereset_pf_c0" and "reset_syn_1" to "corereset_pf_c1" in Instantiating CORERESET_PF section
• Updated "COREJTAGDebug_0" to "corejtagdebug_c0" in Instantiating CoreJTAGDebug section
• Added Instantiating MiV ESS Core section
• In Connecting IP Instances in SmartDesign section:
  • Added Figure 2-22
  • Updated "reset_syn_0" to "CORERESET_PF_C0_0", "reset_syn_1" to "CORERESET_PF_C1_0", "CCC_0_0" to "PF_CCC_C0_0", "COREAXI4INTERCONNECT_C1" to "coreaxi4interconnect_c0_0"
  • Updated Figure 2-23
  • Added MIV_ESS: PCLK in Table 2-1
  • Updated "DDR3_0_0:SYS_reset_N" to "PF_DDR3_C0_0: SYS_RESET_N" and "COREJTAGDebug_0_0" to "COREJTAGDEBUG_C0_0"
  • Updated "CoreJTAGDebug_0_0:TGT_TRSTB_0" to "CoreJTAGDebug_0_0:TGT_TRSTN_0" and "MIV_RV32_C0" to "MIV_RV32_C0_0" in Debug_Target Pin Connection table
  • Added connection description for MiV ESS Core
• Updated "DDR3_0_0" to "PF_DDR3_C0_0" and added a note in Step 10 in Place and Route section
• Updated Figure 2-41 in Serial Terminal Emulation Program (PuTTY) Setup section
• Updated Downloading the Firmware Drivers section
• Updated Figure 3-11 and Figure 3-12 in Creating the main.c File section
• Updated Figure 3-24, peripheral addresses, and Figure 3-25 in Mapping Memory and Peripheral Addresses section
• Added a note in the Building the Mi-V Project section
• Updated Figure 3-29 in Debugging the User Application Using SoftConsole section
• Updated Figure 3-40 in Debugging the User Application from DDR3 Memory section
• Updated FlashPro Express to FPExpress, Figure 4-2, and Figure 4-3 in Appendix 1: Programming the Device using FlashPro Express

• Document migrated from Microsemi template to Microchip template.
• Document number was changed to DS-00004997A from TU0775.
• Updated the document for Libero v2023.1.

• LSRAM was renamed to TCM throughout the document.
• Added Figure 2-4.
• Updated the reason for using the CoreAXI4Interconnect IP in Instantiating AXI Interconnect Bus IP.
• Updated the start and end addresses of AXI4 Slave0 port in Instantiating AXI Interconnect Bus IP.
• Updated Figure 2-8.
• Updated the SYS_CLK_FREQ macro definition from 111111000UL to 83333000UL, see Mapping Memory and Peripheral Addresses.

• Updated for Libero SoC v2021.1.
• Updated Table .
• Added Appendix 2 - DDR3 Configuration.

• Updated Figure 1-1.
• Replaced Figure 2-4.
• Removed sections Instantiating On-chip SRAM, Instantiating the AXI3 to AHB-Lite Bridge, Instantiating the AHB-Lite Bus, and Instantiating the AHB-Lite to APB3 Bridge.
• Updated section Connecting IP Instances in SmartDesign.

• Updated for Libero SoC v12.2.
• Updated the design for AXI-based Mi-V Soft Processor for an enhanced performance with DDR memories.
• Removed Libero SoC and SoftConsole version numbers.

Added Fabric RAMs Initialization.

The document was updated for Libero SoC v12.0.

• Added Design Description.
• The document was updated for Libero SoC PolarFire v2.1.

The document was updated for the Mi-V processor upgrade.

The document was updated for Libero SoC PolarFire v2.0 and SoftConsole v5.2. For more information, see Building the User Application Using SoftConsole.

Information about TCM initialization from external SPI flash was added. For more information, see Configure Design Initialization Data and Memories.