AN4997

2.7 Running the Libero Design Flow

This section describes the Libero® design flow, which involves the following steps:

Synthesis
Place and Route
Verify Timing
Generate FPGA Array Data
Configure Design Initialization Data and Memories
Generate Design Initialization Data
Generate Bitstream
Run PROGRAM Action
Generate SPI Flash Image
Run PROGRAM_SPI_IMAGE Action

After each step is completed, a green tick mark appears next to the step on the Design Flow tab.

Important: To initialize the TCM in PolarFire using the system controller, a local parameter l_cfg_hard_tcm0_en, in the miv_rv32_subsys_pkg.v file must be changed to 1’b1 prior to synthesis. See the TCM section in the MIV_RV32 Handbook.

The online versions of the documents are provided as a courtesy. Verify all content and data in the device’s PDF documentation found on the device product page.