38.4.1 External Clock/Oscillator Timing Requirements

Figure 38-5. Clock Timing

Note: See the table below.

Table 38-7.
Standard Operating Conditions (unless otherwise stated)
Param No.	Sym.	Characteristic	Min.	Typ. †	Max.	Units	Conditions
ECL Oscillator
OS1	F_ECL	Clock Frequency	—	—	500	kHz
OS2	T_{ECL_DC}	Clock Duty Cycle	40	—	60	%
ECM Oscillator
OS3	F_ECM	Clock Frequency	—	—	8	MHz
OS4	T_{ECM_DC}	Clock Duty Cycle	40	—	60	%
ECH Oscillator
OS5	F_ECH	Clock Frequency	—	—	64	MHz
OS6	T_{ECH_DC}	Clock Duty Cycle	40	—	60	%
LP Oscillator
OS7	F_LP	Clock Frequency	—	—	100	kHz	Note 4
XT Oscillator
OS8	F_XT	Clock Frequency	—	—	4	MHz	Note 4
HS Oscillator
OS9	F_HS	Clock Frequency	—	—	20	MHz	V_DD> 2.5V, Note 4
Secondary Oscillator
OS10	F_SEC	Clock Frequency	32.4	32.768	33.1	kHz	Note 4
System Oscillator
OS20	F_OSC	System Clock Frequency	—	—	64	MHz	(Note 2, Note 3)
OS21	F_CY	Instruction Frequency	—	F_OSC/4	—	MHz
OS22	T_CY	Instruction Period	62.5	1/F_CY	—	ns
Note: Instruction cycle period (TCY) equals four times the input oscillator time base period. All specified values are based on characterization data for that particular oscillator type under standard operating conditions with the device executing code. Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current consumption. All devices are tested to operate at “min” values with an external clock applied to OSC1 pin. When an external clock input is used, the “max” cycle time limit is “DC” (no clock) for all devices. The system clock frequency (FOSC) is selected by the “main clock switch controls” as described in the “Power Saving Operation Modes” section. The system clock frequency (FOSC) must meet the voltage requirements defined in the "Standard Operating Conditions" section. LP, XT and HS oscillator modes require an appropriate crystal or resonator to be connected to the device. For clocking the device with the external square wave, one of the EC mode selections must be used.