2.2.3 Protocol 1 and 2 Combinations
The following table lists the protocol combinations that are feasible within a single High Speed Serial Interface block.
| Protocol Type | Protocol # | Lane Width | Lane Assignment | Description | Speed Choices |
|---|---|---|---|---|---|
| PCIe | Protocol 1 | x1 | Lane 0 | — | Gen1 (2.5 Gbps), Gen2 (5.0 Gbps) |
| x2 | Lane 0, Lane 1 | ||||
| x4 | Lane 0, Lane 1, Lane 2, Lane 3 | ||||
| PCIe Reverse | Protocol 1 | x2 | Lane 2, Lane 3 | — | Gen1 (2.5 Gbps), Gen2 (5.0 Gbps) |
| x4 | Lane 0, Lane 1, Lane 2, Lane 3 | ||||
| XAUI | Protocol 1 | x4 | Lane 0, Lane 1, Lane 2, Lane 3 | — | 3.125 Gpbs |
| EPCS | Protocol 1 | x1 | Lane 0, 1, 2 or 3 | — | Custom Speed |
| x2 | Lane 0, Lane 1 | ||||
| x4 | Lane 0, Lane 1, Lane 2, Lane 3 | ||||
| Protocol 2 | x1 | Lane 2 or 3 | Available only when Protocol 1 is selected as PCIe, PCIe Reverse or EPCS | ||
| x2 | Lane 2, Lane 3 |