2.9.4 Polling Cycle/SRC Calibration

Generally, the tolerance of the slow RC (SRC) oscillator is approximately ±10% over temperature drift and voltage range (see parameter no. 14.20 in Electrical Characteristics). The polling cycle calibration procedure is intended to ensure a high accuracy of ±2% of the configured polling cycle when the slow RC (SRC) oscillator is used as the clock source for Timer1.

During the firmware-driven calibration process, the frequency deviation of the SRC oscillator is determined in relation to its nominal frequency of 125 kHz. Timer2 and Timer3, with the XTO as the reference clock, are used to determine a deviation value, which serves as the basis for calculating a proper polling cycle calibration value. This value is stored to the calib.srcCorVal SRAM variable.

Address

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

0x02DD

srcCorVal

Correction value for T1COR

The Timer1 Compare Register (T1COR) is corrected based on the determined calibration value, resulting in polling cycle accuracy of ±2% (see parameter no. 14.20 in Electrical Characteristics). To read out the calib.srcCorVal value, the “Read SRAM/Register” SPI command can be used.

A polling cycle calibration process can be triggered at the following time points:

  • After power-on during system initialization when enabled in eepConfValid.confInitFlags.SRC.
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
0x0008 confInitFlags AntTune TempMeas SRC FRC ————
  • During the periodic self-check in PollingMode or during a self-check that is started by using the “Calibrate and Check” SPI command where this is enabled in eepTrxCal.calConf1.EN_SRCCAL.
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
0x001C calConf1 —EN_TEMP_MEAS EN_SRCCAL EN_FRCCAL ———EN_REGREFRESH
  • From IDLEMode via the “Calibrate and Check” SPI command if the EN_SRCCAL bit in tuneCheckConfig is set to ‘1’ (see Calibrate and Check).
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
tuneCheckConfig EN_ANT_TUNE EN_TEMP_MEAS EN_SRCCAL EN_FRCCAL EN_VCOCAL —EN_SELFCHECK —

Setting the SRC_CAL bit within the eepEventConf.cmdRdyConf command-ready variable to ‘1’ raises a command-ready (CMD_RDY) event on the event pin PB6 after the polling cycle calibration process finishes.

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
0x0096 cmdRdyConf ANT_TUNE TEMP_MEAS SRC_CAL FRC_CAL VCO_CAL RF_CAL SELFCHECK TX

The polling cycle calibration requires additional time, see Timing Characteristics.