2.9.5 FRC Calibration

Generally, the tolerance of the fast RC (FRC) oscillator is ±5% over temperature drift and voltage range (see parameter no. 14.30 in Electrical Characteristics).

Tolerance of ±2% is required to be able to use the FRC oscillator as a timer/system clock source.

The firmware-driven calibration routine of the FRC is based on the XTO frequency. The frcCalibGate setting located in EEPROM defines an XTO-based gate.

Address

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

0x0098

frcCalibGate

data[7:0]

The gate time is calculated so that it always results in a length of 200 periods in relation to a nominal clock frequency of 6.36 MHz. During the open gate time, the number of FRC pulses is counted. The result of this counting process serves as the basis for calculating the new FRC oscillator calibration bits of the FRCCAL hardware register, as described in System Clock Register Description. This register has a direct influence on the FRC frequency.

Note: The FRC is only tested in the production test for FRCCAL values required for achieving 6.36 MHz. No other frequencies are used.

An FRC calibration process can be triggered at the following time points:

  • After power-on during system initialization when enabled in eepConfValid.confInitFlags.FRC.

Address

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

0x0008

confInitFlags

AntTune

TempMeas

SRC

FRC

————

During the periodic self-check in PollingMode or during a self-check that is started by using the “Calibrate and Check” SPI command if enabled in eepTrxCal.calConf1.EN_FRCCAL.

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
0x001C calConf1 —EN_TEMP_MEAS EN_SRCCAL EN_FRCCAL ———EN_REGREFRESH
  • From IDLEMode via the “Calibrate and Check” SPI command if the EN_FRCCAL bit in tuneCheckConfig is set to ‘1’ (see Calibrate and Check).
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
tuneCheckConfig EN_ANT_TUNE EN_TEMP_MEAS EN_SRCCAL EN_FRCCAL EN_VCOCAL —EN_SELFCHECK —

Setting the FRC_CAL bit within the eepEventConf.cmdRdyConf command-ready variable to ‘1’ raises a command-ready (CMD_RDY) event on the event pin PB6 after the FRC calibration process has finished.

Address

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

0x0096

cmdRdyConf

ANT_TUNE

TEMP_MEAS

SRC_CAL

FRC_CAL

VCO_CAL

RF_CAL

SELFCHECK

TX

The FRC calibration requires additional time, see Timing Characteristics.