25.6.2.1 Initialization

The EIC must be initialized in the following order:

1. Enable CLK_EIC_APB.
2. Enable GCLK_EIC or CLK_ULP32K when one of the following configuration is selected:
   • The NMI uses edge detection or filtering.
   • One or more EXTINT uses filtering.
   • One or more EXTINT uses edge detection.
   • One or more EXTINT uses debouncing.

   GCLK_EIC is used when a frequency higher than 32.768 kHz is required for filtering.

   CLK_ULP32K is recommended when power consumption is the priority. For CLK_ULP32K write a '1' to the Clock Selection bit in the Control A register (CTRLA.CKSEL).

3. Configure the EIC input sense and filtering by writing the configuration register (CONFIG0 or CONFIG1).
4. Optionally, enable the Asynchronous mode.
5. Optionally, enable the Debouncer mode.
6. Enable the EIC by writing a ‘1’ to CTRLA.ENABLE.
7. Wait for SYNCBUSY.ENABLE = 1. Level detection is now functional. Edge detection will be functional after three cycles of the selected GCLK (GCLK_EIC or CLK_ULP32K).
8. If required, configure the NMI by writing the Non-Maskable Interrupt Control register (NMICTRL).

The following bits are enable-protected, that is, it can only be written when the EIC is disabled (CTRLA.ENABLE = 0):

• The Clock Selection bit in the Control A register (CTRLA.CKSEL)

The following registers are enable-protected:

The Enable-Protected bits in the CTRLA register can be written simultaneously when setting the CTRLA.ENABLE to '1', but not simultaneously as the CTRLA.ENABLE is being cleared.

Enable-protection is denoted by the "Enable-Protected" property in the register description.