16.6.1 Principle of Operation

The OSC32KCTRL bus clock (CLK_OSC32KCTRL_APB) is required to access the OSC32KCTRL register. This clock must be enabled in the MCLK - Main Clock.

The OSC32KCTRL gathers controls for the XOSC32K, OSC32K, and OSCULP32K 32.768 kHz oscillators and provides these clock sources to the Generic Clock Controller (GCLK), Real-Time Counter (RTC), and Watchdog Timer (WDT).

Through this interface, the sub-peripherals are enabled, disabled, or have their calibration values updated.

The STATUS register gathers different status signals coming from the sub-peripherals of the OSC32KCTRL Control register. The status signals can be used to generate system interrupts, and in some cases wake up the system from Standby mode, provided the corresponding interrupt is enabled.