16.6.4 32.768 kHz Internal Oscillator (OSC32K) Operation
The OSC32K provides a tunable, low-speed, and low-power clock source.
At reset, the OSC32K is disabled. It can be enabled by setting the Enable bit in the 32.768 kHz Internal Oscillator Control register (OSC32K.ENABLE = 1). The OSC32K is disabled by clearing the Enable bit in the 32.768 kHz Internal Oscillator Control register (OSC32K.ENABLE = 0).
The frequency of the OSC32K oscillator is controlled by OSC32K.CALIB. Before using the OSC32K, this Calibration field must be loaded with production calibration values from the NVM Software Calibration Area. When writing the Calibration bits, the user must wait for the STATUS.OSC32KRDY bit to go high before the new value is committed to the oscillator.
The OSC32K has a 32.768 kHz output which is enabled by setting the EN32K bit in the 32.768 kHz Internal Oscillator Control register (OSC32K.EN32K = 1). The OSC32K also has a 1.024 kHz clock output. This is enabled by setting the EN1K bit in the 32.768 kHz Internal Oscillator Control register (OSC32K.EN1K).
The OSC32K will behave differently in different sleep modes based on the settings of OSC32K.RUNSTDBY, OSC32K.ONDEMAND, and OSC32K.ENABLE. If OSC32KCTRL.ENABLE = 0, the OSC32K will be always stopped. For OS32KCTRL.ENABLE = 1, this table is valid:
| CPU Mode | OSC32KCTRL.RUNSTDBY | OSC32KCTRL.ONDEMAND | Sleep Behavior |
|---|---|---|---|
| Active or Idle | - | 0 | Always run |
| Active or Idle | - | 1 | Run if requested by peripheral |
| Standby | 1 | 0 | Always run |
| Standby | 1 | 1 | Run if requested by peripheral |
| Standby | 0 | - | Run if requested by peripheral |
The OSC32K requires a start-up time. For this reason, OSC32K will keep running across resets when OSC32K.ONDEMAND = 0, except for Power-on Reset (POR).
After such a reset, or when waking up from a Sleep mode where the OSC32K was disabled, the OSC32K will need time to stabilize on the correct frequency.
This startup time can be configured by changing the Oscillator Start-Up Time bit group (OSC32K.STARTUP) in the OSC32K Control register. During the start-up time, the oscillator output is masked to ensure that no unstable clock propagates to the digital logic.
Once the oscillator is stable and ready to be used as a clock source, the OSC32K Ready bit in the Status register is set (STATUS.OSC32KRDY=1). The transition of STATUS.OSC32KRDY from '0' to '1' generates an interrupt if the OSC32K Ready bit in the Interrupt Enable Set register is set (INTENSET.OSC32KRDY = 1).
The OSC32K can be used as a source for Generic Clock Generators (GCLK) or for the Real-Time Counter (RTC). Before enabling the GCLK or the RTC module, the corresponding oscillator output must be enabled (OSC32K.EN32K or OSC32K.EN1K) in order to ensure proper operation. In the same way, the GCLK or RTC modules must be disabled before the clock selection is changed.