14.7.1 Control A
| Name: | CTRLA |
| Offset: | 0x00 |
| Reset: | 0x00 |
| Property: | PAC Write-Protection, Write-Synchronized Bits |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| SWRST | |||||||||
| Access | R/W | ||||||||
| Reset | 0 |
Bit 0 – SWRST Software Reset
Writing a zero to this bit has no effect.
Setting this bit to ‘1’ will reset all registers in the GCLK to their initial state after a Power Reset, except for generic clocks and associated Generators that have their WRTLOCK bit in PCHCTRLm set to ‘1’.
Refer to GENCTRL Reset Value for details on GENCTRLn register reset.
Refer to PCHCTRL Reset Value for details on PCHCTRLm register reset.
Note: CTRLA.SWRST is a write-synchronized bit: SYNCBUSY.SWRST must be checked to ensure
the CTRLA.SWRST synchronization is complete.
| Value | Description |
|---|---|
| 0 | There is no Reset operation ongoing. |
| 1 | A Reset operation is ongoing. |