26.5.12 Debug Operation

When an external debugger forces the CPU into debug mode, the peripheral continues normal operation. DBGCTRL.DBGECC allows configuring the effects of the debugger reads in Flash memory.

Access to the NVM block can be protected by the security bit (which implies sending the Set Security Bit command and resetting the device for the protection to be applied). In this case, the NVM block will not be accessible through the debugger (Impossible to read or write. Erase will be possible only through a chip erase command, provided the Chip Erase Hard Lock bit has not been set). See the section on the NVMCTRL 26.5.8 Security Bit and Chip Erase Hard Lock Bit and the Device Service Unit for details.