26.5.3 Clocks

Two synchronous clocks are used by the NVMCTRL. One is provided by the AHB bus (CLK_NVMCTRL_AHB) and the other is provided by the APB bus (CLK_NVMCTRL_APB). The AHB bus and clock are used for all direct memory access, while the APB is used for the control and command interface. For higher system frequencies, a specific number of wait states has to be configured in CTRLB.RWS. Refer to the Electrical Characteristics for the exact number of wait states to be used for a particular frequency range. When changing the AHB bus frequency, the user shall ensure that the NVM Controller is configured with the proper number of wait states. For example when switching to a higher AHB frequency, the number of wait states shall be adapted to the future frequency first, and then only can the frequency be increased to the new value.