38.7.12 Comparator Control n


Bit	31	30	29	28	27	26	25	24
			OUT[1:0]			FLEN[2:0]
Access			R/W	R/W		R/W	R/W	R/W
Reset			0	0		0	0	0


Bit	23	22	21	20	19	18	17	16
					HYSTEN		SPEED[1:0]
Access					R/W		R/W	R/W
Reset					0		0	0


Bit	15	14	13	12	11	10	9	8
	SWAP	MUXPOS[2:0]				MUXNEG[2:0]
Access	R/W	R/W	R/W	R/W		R/W	R/W	R/W
Reset	0	0	0	0		0	0	0


Bit	7	6	5	4	3	2	1	0
		RUNSTDBY		INTSEL[1:0]		SINGLE	ENABLE
Access		R/W		R/W	R/W	R/W	R/W
Reset		0		0	0	0	0

Bits 29:28 – OUT[1:0] Output

These bits configure the output selection for comparator n. COMPCTRLn.OUT can be written only while COMPCTRLn.ENABLE is zero.

Note: For internal use of the comparison results by the CCL, this bit must be 0x1 or 0x2.

Note: This bit field is enable-protected. This bit field is not synchronized.

Value	Name	Description
0x0	OFF	The output of COMPn is not routed to the COMPn I/O port
0x1	ASYNC	The asynchronous output of COMPn is routed to the COMPn I/O port
0x2	SYNC	The synchronous output (including filtering) of COMPn is routed to the COMPn I/O port
0x3	N/A	Reserved

Bits 26:24 – FLEN[2:0] Filter Length

These bits configure the filtering for comparator n. COMPCTRLn.FLEN can only be written while COMPCTRLn.ENABLE is zero.

Note: This bit field is enable-protected. This bit field is not synchronized.

Value	Name	Description
0x0	OFF	No filtering
0x1	MAJ3	3-bit majority function (2 of 3)
0x2	MAJ5	5-bit majority function (3 of 5)
0x3-0x7	N/A	Reserved

Bit 19 – HYSTEN Hysteresis Enable

This bit indicates the hysteresis mode of comparator n. Hysteresis is available only for continuous mode (COMPCTRLn.SINGLE=0).

Note: This bit is enable-protected. This bit is not synchronized.

Value	Description
0	Hysteresis is disabled.
1	Hysteresis is enabled.

Bits 17:16 – SPEED[1:0] Speed Selection

This bit indicates the speed/propagation delay mode of comparator n. COMPCTRLn.SPEED can be written only while COMPCTRLn.ENABLE is zero.

Note: This bit field is enable-protected. This bit field is not synchronized.


Value	Name	Description
0x0	LOW	Low speed
0x3	HIGH	High speed

Bit 15 – SWAP Swap Inputs and Invert

This bit swaps the positive and negative inputs to COMPn and inverts the output. This function can be used for offset cancellation. COMPCTRLn.SWAP can be written only while COMPCTRLn.ENABLE is zero.

Note: This bit is enable-protected. This bit is not synchronized.

Value	Description
0	The output of MUXPOS connects to the positive input, and the output of MUXNEG connects to the negative input.
1	The output of MUXNEG connects to the positive input, and the output of MUXPOS connects to the negative input.

Bits 14:12 – MUXPOS[2:0] Positive Input Mux Selection

These bits select which input will be connected to the positive input of comparator n. COMPCTRLn.MUXPOS can be written only while COMPCTRLn.ENABLE is zero.

Note: This bit field is enable-protected. This bit field is not synchronized.


Value	COMP0/1	COMP2/3	Description
0x0	AIN0	AIN4	AC input
0x1	AIN1	AIN5	AC input
0x2	AIN2	AIN6	AC input
0x3	AIN3	AIN7	AC input
0x4	VSCALE		VDD Scaler
0x5-0x7	Reserved		Reserved

Bits 10:8 – MUXNEG[2:0] Negative Input Mux Selection

These bits select which input will be connected to the negative input of comparator n. COMPCTRLn.MUXNEG can only be written while COMPCTRLn.ENABLE is zero.

Note: This bit field is enable-protected. This bit field is not synchronized.


Value	COMP0/1	COMP2/3	Description
0x0	AIN0	AIN4	AC input
0x1	AIN1	AIN5	AC input
0x2	AIN2	AIN6	AC input
0x3	AIN3	AIN7	AC input
0x4	GND		Ground
0x5	VSCALE		VDD scaler
0x6	INTREF		Internal voltage reference, supplied by the bandgap (Refer to SUPC.VREF.SEL for voltage level information. Allow 10 µs for the bandgap to stabilize before enabling the AC interrupt or EVSYS event channel.)
0x7	DAC		DAC output (not available on all device variants. Refer to the Configuration Summary chapter for the list of variants embedding the DAC.)

Bit 6 – RUNSTDBY Run in Standby

This bit controls the behavior of the comparator during Standby Sleep mode.

Note: This bit is enable-protected. This bit is not synchronized.

Value	Description
0	The comparator is disabled during sleep.
1	The comparator continues to operate during sleep.

Bits 4:3 – INTSEL[1:0] Interrupt Selection

These bits select the condition for comparator n to generate an interrupt or event. COMPCTRLn.INTSEL can be written only while COMPCTRLn.ENABLE is zero.

Note: This bit field is enable-protected. This bit field is not synchronized.

Value	Name	Description
0x0	TOGGLE	Interrupt on comparator output toggle
0x1	RISING	Interrupt on comparator output rising
0x2	FALLING	Interrupt on comparator output falling
0x3	EOC	Interrupt on end of comparison (single-shot mode only)

Bit 2 – SINGLE Single-Shot Mode

This bit determines the operation of comparator n. COMPCTRLn.SINGLE can be written only while COMPCTRLn.ENABLE is zero.

Note: This bit is enable-protected. This bit is not synchronized.

Value	Description
0	Comparator n operates in continuous measurement mode.
1	Comparator n operates in single-shot mode.

Bit 1 – ENABLE Enable

Writing a zero to this bit disables comparator n. Writing a one to this bit enables comparator n.

Note:

This bit is write-synchronized: SYNCBUSY.COMPCTRL must be checked to ensure the COMPCTRL.ENABLE synchronization is complete.
This bit is not enable-protected.

Name:	COMPCTRLn
Offset:	0x10 + n*0x04 [n=0..3]
Reset:	0x00000000
Property:	PAC Write-Protection, Write-Synchronized Bits