38.7.5 Interrupt Enable Set

This register allows the user to enable an interrupt without doing a read-modify-write operation. Changes in this register will also be reflected in the Interrupt Enable Clear register (INTENCLR).

Name:	INTENSET
Offset:	0x05
Reset:	0x00
Property:	PAC Write-Protection


Bit	7	6	5	4	3	2	1	0
			WIN1	WIN0	COMP3	COMP2	COMP1	COMP0
Access			R/W	R/W	R/W	R/W	R/W	R/W
Reset			0	0	0	0	0	0

Bits 4, 5 – WINx Window x Interrupt Enable [x = 1..0]

Writing a '0' to this bit has no effect.

Writing a '1' to this bit will set the Window x Interrupt Enable bit, which enables the Window x interrupt.

Value	Description
0	The Window x interrupt is disabled.
1	The Window x interrupt is enabled.

Bits 0, 1, 2, 3 – COMPx Comparator x Interrupt Enable [x = 3..0]

Writing a '0' to this bit has no effect.

Writing a '1' to this bit will set the Comparator x Interrupt Enable bit, which enables the Comparator x interrupt.

Value	Description
0	The Comparator x interrupt is disabled.
1	The Comparator x interrupt is enabled.