35.6.2.1 Initialization

The TCC bus clock (CLK_TCCx_APB) is required to access the related TCC registers. This clock can be enabled in the MCLK - Main Clock Module.

The generic clock (GCLK_TCCx) is required to clock the related TCC. This clock must be configured and enabled in the GCLK - Generic Clock Module before using the TCC.

The following registers are enable-protected, that is, they can only be written when the TCC is disabled(CTRLA.ENABLE = 0):
  • The Control A (CTRLA) register, except the Run Standby (RUNSTDBY), Enable (ENABLE) and Software Reset (SWRST) bits
  • The Recoverable Fault n Control registers (FCTRLA and FCTRLB)
  • The Waveform Extension Control register (WEXCTRL)
  • The Drive Control register (DRVCTRL)
  • The Event Control register (EVCTRL)

The Enable-Protected bits in the CTRLA register can be written at the same time as CTRLA.ENABLE is written to '1', but not at the same time as CTRLA.ENABLE is written to '0'. Enable-protection is denoted by the “Enable-Protected” property in the register description.

Before the TCC is enabled, it must be configured as outlined by the following steps:
  1. Enable the TCC bus clock (CLK_TCCx_APB).
  2. If Capture mode is required, enable the channel in Capture mode by writing a '1' to the Capture Enable bit in the Control A register (CTRLA.CPTEN).
Optionally, the following configurations can be set before enabling TCC:
  1. Select PRESCALER setting in the Control A register (CTRLA.PRESCALER).
  2. Select Prescaler Synchronization setting in Control A register (CTRLA.PRESCSYNC).
  3. If down-counting operation is desired, write the Counter Direction bit in the Control B Set register (CTRLBSET.DIR) to '1'. In this case, the COUNT register must be initialized with the desired TOP value.
  4. Select the Waveform Generation operation in the WAVE register (WAVE.WAVEGEN).
  5. Select the Waveform Output Polarity in the WAVE register (WAVE.POL).
  6. The waveform output can be inverted for the individual channels using the Waveform Output Invert Enable bit group in the Driver register (DRVCTRL.INVEN).
Note: Two instances of the TCC (TCC0 and TCC1) may share a peripheral clock channel. In this case, they cannot be set to different clock frequencies. Refer to the peripheral clock channel mapping of the Generic Clock Controller (GCLK.PCHCTRLm) to identify shared peripheral clocks.