35.7 Register Summary

Refer to the Registers Description section for more details on register properties and access permissions.

Important: The peripheral register map is given as an example for CTRLA.RESOLUTION = 0x2 (DITH5) case.

CTRLA.RESOLUTION bit field selection affects the following registers’ bit fields:

COUNT
PER
CCx
PERBUF
CCBUFx

Refer to each register for more information.


Offset	Name	Bit Pos.	7	6	5	4	3	2	1	0
0x00	CTRLA	31:24					CPTEN3	CPTEN2	CPTEN1	CPTEN0
		23:16	DMAOS							FCYCLE
		15:8		ALOCK	PRESCSYNC[1:0]		RUNSTDBY	PRESCALER[2:0]
		7:0		RESOLUTION[1:0]					ENABLE	SWRST
0x04	CTRLBCLR	7:0	CMD[2:0]			IDXCMD[1:0]		ONESHOT	LUPD	DIR
0x05	CTRLBSET	7:0	CMD[2:0]			IDXCMD[1:0]		ONESHOT	LUPD	DIR
0x06 ... 0x07	Reserved
0x08	SYNCBUSY	31:24
		23:16
		15:8					CC3	CC2	CC1	CC0
		7:0	PER	WAVE	PATT	COUNT	STATUS	CTRLB	ENABLE	SWRST
0x0C	FCTRLA	31:24					FILTERVAL[3:0]
		23:16	BLANKVAL[7:0]
		15:8	BLANKPRESC	CAPTURE[2:0]			CHSEL[1:0]		HALT[1:0]
		7:0	RESTART	BLANK[1:0]		QUAL	KEEP		SRC[1:0]
0x10	FCTRLB	31:24					FILTERVAL[3:0]
		23:16	BLANKVAL[7:0]
		15:8	BLANKPRESC	CAPTURE[2:0]			CHSEL[1:0]		HALT[1:0]
		7:0	RESTART	BLANK[1:0]		QUAL	KEEP		SRC[1:0]
0x14	WEXCTRL	31:24	DTHS[7:0]
		23:16	DTLS[7:0]
		15:8					DTIEN3	DTIEN2	DTIEN1	DTIEN0
		7:0							OTMX[1:0]
0x18	DRVCTRL	31:24	FILTERVAL1[3:0]				FILTERVAL0[3:0]
		23:16	INVEN7	INVEN6	INVEN5	INVEN4	INVEN3	INVEN2	INVEN1	INVEN0
		15:8	NRV7	NRV6	NRV5	NRV4	NRV3	NRV2	NRV1	NRV0
		7:0	NRE7	NRE6	NRE5	NRE4	NRE3	NRE2	NRE1	NRE0
0x1C ... 0x1D	Reserved
0x1E	DBGCTRL	7:0						FDDBD		DBGRUN
0x1F	Reserved
0x20	EVCTRL	31:24					MCEO3	MCEO2	MCEO1	MCEO0
		23:16					MCEI3	MCEI2	MCEI1	MCEI0
		15:8	TCEI1	TCEI0	TCINV1	TCINV0		CNTEO	TRGEO	OVFEO
		7:0	CNTSEL[1:0]		EVACT1[2:0]			EVACT0[2:0]
0x24	INTENCLR	31:24
		23:16					MC3	MC2	MC1	MC0
		15:8	FAULT1	FAULT0	FAULTB	FAULTA	DFS	UFS
		7:0					ERR	CNT	TRG	OVF
0x28	INTENSET	31:24
		23:16					MC3	MC2	MC1	MC0
		15:8	FAULT1	FAULT0	FAULTB	FAULTA	DFS	UFS
		7:0					ERR	CNT	TRG	OVF
0x2C	INTFLAG	31:24
		23:16					MC3	MC2	MC1	MC0
		15:8	FAULT1	FAULT0	FAULTB	FAULTA	DFS	UFS
		7:0					ERR	CNT	TRG	OVF
0x30	STATUS	31:24					CMP3	CMP2	CMP1	CMP0
		23:16					CCBUFV3	CCBUFV2	CCBUFV1	CCBUFV0
		15:8	FAULT1	FAULT0	FAULTB	FAULTA	FAULT1IN	FAULT0IN	FAULTBIN	FAULTAIN
		7:0	PERBUFV		PATTBUFV		DFS	UFS	IDX	STOP
0x34	COUNT	31:24
		23:16	COUNT[23:16]
		15:8	COUNT[15:8]
		7:0	COUNT[7:0]
0x38	PATT	15:8	PGV7	PGV6	PGV5	PGV4	PGV3	PGV2	PGV1	PGV0
0x38	PATT	7:0	PGE7	PGE6	PGE5	PGE4	PGE3	PGE2	PGE1	PGE0
0x3A ... 0x3B	Reserved
0x3C	WAVE	31:24					SWAP3	SWAP2	SWAP1	SWAP0
		23:16					POL3	POL2	POL1	POL0
		15:8					CICCEN3	CICCEN2	CICCEN1	CICCEN0
		7:0	CIPEREN	RAMP[2:0]				WAVEGEN[2:0]
0x40	PER	31:24
		23:16	PER[17:10]
		15:8	PER[9:2]
		7:0	PER[1:0]		DITHER[5:0]
0x44	CC0	31:24
		23:16	CC[17:10]
		15:8	CC[9:2]
		7:0	CC[1:0]		DITHER[5:0]
0x48	CC1	31:24
		23:16	CC[17:10]
		15:8	CC[9:2]
		7:0	CC[1:0]		DITHER[5:0]
0x4C	CC2	31:24
		23:16	CC[17:10]
		15:8	CC[9:2]
		7:0	CC[1:0]		DITHER[5:0]
0x50	CC3	31:24
		23:16	CC[17:10]
		15:8	CC[9:2]
		7:0	CC[1:0]		DITHER[5:0]
0x54 ... 0x63	Reserved
0x64	PATTBUF	15:8	PGVB7	PGVB6	PGVB5	PGVB4	PGVB3	PGVB2	PGVB1	PGVB0
0x64	PATTBUF	7:0	PGEB7	PGEB6	PGEB5	PGEB4	PGEB3	PGEB2	PGEB1	PGEB0
0x66 ... 0x6B	Reserved
0x6C	PERBUF	31:24
		23:16	PERBUF[17:10]
		15:8	PERBUF[9:2]
		7:0	PERBUF[1:0]		DITHERBUF[5:0]
0x70	CCBUF0	31:24
		23:16	CCBUF[17:10]
		15:8	CCBUF[9:2]
		7:0	CCBUF[1:0]		DITHERBUF[5:0]
0x74	CCBUF1	31:24
		23:16	CCBUF[17:10]
		15:8	CCBUF[9:2]
		7:0	CCBUF[1:0]		DITHERBUF[5:0]
0x78	CCBUF2	31:24
		23:16	CCBUF[17:10]
		15:8	CCBUF[9:2]
		7:0	CCBUF[1:0]		DITHERBUF[5:0]
0x7C	CCBUF3	31:24
		23:16	CCBUF[17:10]
		15:8	CCBUF[9:2]
		7:0	CCBUF[1:0]		DITHERBUF[5:0]