44.5.1 Control Register
| Name: | CTRL |
| Offset: | 0x00 |
| Reset: | 0x00000000 |
| Property: | PAC Write-Protection |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| Access | |||||||||
| Reset |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| Access | |||||||||
| Reset |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| SMBISTP2 | SMBISTP1 | ||||||||
| Access | R/W | R/W | |||||||
| Reset | 0 | 0 |
Bit 1 – SMBISTP2 SRAM MBIST Partition 2 test start
Writing '1' in this bit triggers the testing of SRAM Partition 2.
Bit 0 – SMBISTP1 SRAM MBIST Partition 1 test start
Writing '1' in this bit triggers the testing of SRAM Partition 1.