19.5.3.3 Sleep Mode Controller

A Sleep mode is entered by executing the Wait For Interrupt instruction (WFI). The Sleep Mode bits in the Sleep Configuration register (SLEEPCFG.SLEEPMODE) select the level of the Sleep mode. Before entering any sleep mode, ensure any commands written to the NVM controller have completed by confirming the NVMCTRL INTFLAG.READY bit is '1'.

Note: A small latency happens between the store instruction and actual writing of the SLEEPCFG register due to bridges. Software must ensure that the SLEEPCFG register reads the desired value before issuing a WFI instruction.

Table 19-1. Sleep Mode Entry and Exit Table
Mode	Mode Entry	Wake-Up Sources
IDLE0	SLEEPCFG.SLEEPMODE = IDLE0	Synchronous ⁽²⁾ (CAN included), asynchronous ⁽¹⁾
IDLE2	SLEEPCFG.SLEEPMODE = IDLE2	Synchronous ⁽²⁾ (CAN excluded), asynchronous ⁽¹⁾
STANDBY	SLEEPCFG.SLEEPMODE = STANDBY	Synchronous⁽³⁾ (CAN excluded), Asynchronous⁽¹⁾

Note:

Asynchronous: interrupt generated on GCLK generic clock, external clock, or external event.
Synchronous: interrupt generated on the APB clock.
Synchronous interrupt only for peripherals configured to run in standby.

Note: The type of wake-up sources (synchronous or asynchronous) is given in each module interrupt section.

The sleep modes (idle, standby) and their effect on the clocks activity, the regulator and the SRAM state are described in the table and the sections below.

Table 19-2. Sleep Mode Overview
Mode	CPU clock	AHB/APB clocks	Main clock	GCLK0 clock	GCLK1-8 clocks	Clock Sources		Regulator	SRAM
Mode	CPU clock	AHB/APB clocks	Main clock	GCLK0 clock	GCLK1-8 clocks	ONDEMAND = 0	ONDEMAND = 1	Regulator	SRAM
IDLE0	Stop	Run⁽¹⁾, CAN included	Run	Run	Run/Stop ⁽³⁾	Run	Run/Stop ⁽⁴⁾	Main	Normal
IDLE2	Stop	Run⁽²⁾, CAN excluded	Run	Run	Run/Stop ⁽³⁾	Run	Run/Stop ⁽⁴⁾	Main	Normal
STANDBY	Stop	Stop⁽⁵⁾	Stop ⁽⁵⁾	Stop if RUNSTDBY = 0		Stop if RUNSTDBY=0		LPVREG ⁽⁸⁾	Low Power ⁽⁹⁾
STANDBY	Stop	Stop⁽⁵⁾	Stop ⁽⁵⁾	Stop/Run if RUNSTDBY=1 ⁽⁶⁾		Run if RUNSTDBY=1	Stop/Run if RUNSTDBY=1 ⁽⁷⁾	LPVREG ⁽⁸⁾	Low Power ⁽⁹⁾

Note:

The AHB/APB clocks are running up to MCLK, and then provided only to the IPs requesting them and to the CAN (which is a specific IP with no clock request mechanism). For the other IPs not requesting their AHB/APB clocks, these are gated at MCLK output.
The AHB/APB clocks are running up to MCLK, and then provided only to the IPs requesting them. For the CAN and for the other IPs not requesting the clocks, they are gated at MCLK output.
Each GCLK1 to GCLK8 is running if the associated generated clock is requested by at least one IP. It is stopped if no IP is requesting this clock.
The clock source is running if the clock is requested by at least one GCLK Generator. It is stopped if no GCLK Generator is requesting this clock and will be restarted as soon as an IP requests a clock coming from a GCLK fed by this clock source.
The AHB/APB clocks are stopped, except if requested by at least one IP, and in this case, only provided to this/these IP(s) through GCLK0 and MCLK.
Each GCLK generators is stopped, except if the clock it generates is requested by at least one IP.
Each Clock Source is stopped, except if the clock it generates is requested by at least one GCLK Generator.
Regulator state is programmable by using STDBYCFG.VREGSMOD bits.
SRAM state is programmable by using STDBYCFG.BBIASHS bit.