42.6.2.1 Initialization

The PDEC bus clock (CLK_PDEC_APB) is required to access the PDEC registers. This clock can be enabled in the MCLK - Main Clock module.

A generic clock (GCLK_PDEC) is required to clock the PDEC. This clock must be configured and enabled in the GCLK - Generic Clock Controller before using the PDEC.

The following PDEC registers are enable-protected, that is, they can only be written when the PDEC is disabled (CTRLA.ENABLE is zero):

• The Event Control register (EVCTRL)

Enable-protection is denoted by the 'Enable-Protected' property in the register description.

The following register bits are enable-protected, meaning that they can only be written when the PDEC is disabled (CTRLA.ENABLE = 0):

• The Maximum Consecutive Missing Pulses bits in the Control A register (CTRLA.MAXCMP[3:0])
• The Angular Counter Length bits in the Control A register (CTRLA.ANGULAR[2:0])
• The I/O Pin x Invert Enable bits in the Control A register (CTRLA.PINVEN[2:0])
• The PDEC Input From Pin x Enable bits in the Control A register (CTRLA.PINEN[2:0])
• The Period Enable bit in the Control A register (CTRLA.PEREN)
• The PDEC Phase A and B Swap bit in the Control A register (CTRLA.SWAP)
• The Auto Lock bit in the Control A register (CTRLA.ALOCK)
• The PDEC Configuration bits in the Control A register (CTRLA.CONF[2:0])
• The Run in Standby bit in the Control A register (CTRLA.RUNSTDBY)
• The Operation Mode bits in the Control A register (CTRLA.MODE[1:0])
• The Enable-protected bits in the CTRLA register can be written simultaneously as CTRLA.ENABLE is written to '1', but not at the same time as CTRLA.ENABLE is written to '0'