28.6.7 Channel n Control

This register allows the user to configure channel n. To write to this register, do a single, 32-bit write of all the configuration data.

Name:	CHANNELn
Offset:	0x20 + n*0x04 [n=0..11]
Reset:	0x00008000
Property:	PAC Write-Protection


Bit	31	30	29	28	27	26	25	24

Access
Reset


Bit	23	22	21	20	19	18	17	16

Access
Reset


Bit	15	14	13	12	11	10	9	8
	ONDEMAND	RUNSTDBY			EDGSEL[1:0]		PATH[1:0]
Access	R/W	R/W			R/W	R/W	R/W	R/W
Reset	1	0			0	0	0	0


Bit	7	6	5	4	3	2	1	0
		EVGEN[6:0]
Access		R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset		0	0	0	0	0	0	0

Bit 15 – ONDEMAND Generic Clock On Demand

Value	Description
0	Generic clock for a channel is always on, if the channel is configured and generic clock source is enabled.
1	Generic clock is requested on demand while an event is handled

Bit 14 – RUNSTDBY Run in Standby

This bit is used to define the behavior during standby sleep mode.

Value	Description
0	The channel is disabled in standby sleep mode.
1	The channel is not stopped in standby sleep mode and depends on the CHANNEL.ONDEMAND

Bits 11:10 – EDGSEL[1:0] Edge Detection Selection

These bits set the type of edge detection to be used on the channel.

These bits must be written to zero when using the asynchronous path.

Value	Name	Description
0x0	NO_EVT_OUTPUT	No event output when using the resynchronized or synchronous path
0x1	RISING_EDGE	Event detection only on the rising edge of the signal from the event generator
0x2	FALLING_EDGE	Event detection only on the falling edge of the signal from the event generator
0x3	BOTH_EDGES	Event detection on rising and falling edges of the signal from the event generator

Bits 9:8 – PATH[1:0] Path Selection

These bits are used to choose which path will be used by the selected channel.

The path choice can be limited by the channel source, see the table in USERm.

Value	Name	Description
0x0	SYNCHRONOUS	Synchronous path
0x1	RESYNCHRONIZED	Resynchronized path
0x2	ASYNCHRONOUS	Asynchronous path
0x3	-	Reserved

Bits 6:0 – EVGEN[6:0] Event Generator

These bits are used to choose the event generator to connect to the selected channel.

Table 28-2. Event Generators ⁽¹⁾
Value	Event Generator	Description
0x00	NONE	No event generator selected
0x01	RTC PERD	RTC Periodic daily event
0x02	Reserved	Reserved
0x03	OSCCTRL FAIL	XOSC Clock Failure
0x04	OSC32KCTRL FAIL	XOSC32K Clock Failure
0x05	RTC CMP0	Compare 0 (mode 0 and 1) or Alarm 0 (mode 2)
0x06	RTC CMP1	Compare 1
0x07	RTC OVF	Overflow
0x08	RTC PER0	Period 0
0x09	RTC PER1	Period 1
0x0A	RTC PER2	Period 2
0x0B	RTC PER3	Period 3
0x0C	RTC PER4	Period 4
0x0D	RTC PER5	Period 5
0x0E	RTC PER6	Period 6
0x0F	RTC PER7	Period 7
0x10	EIC EXTINT0	External Interrupt 0
0x11	EIC EXTINT1	External Interrupt 1
0x12	EIC EXTINT2	External Interrupt 2
0x13	EIC EXTINT3	External Interrupt 3
0x14	EIC EXTINT4	External Interrupt 4
0x15	EIC EXTINT5	External Interrupt 5
0x16	EIC EXTINT6	External Interrupt 6
0x17	EIC EXTINT7	External Interrupt 7
0x18	EIC EXTINT8	External Interrupt 8
0x19	EIC EXTINT9	External Interrupt 9
0x1A	EIC EXTINT10	External Interrupt 10
0x1B	EIC EXTINT11	External Interrupt 11
0x1C	EIC EXTINT12	External Interrupt 12
0x1D	EIC EXTINT13	External Interrupt 13
0x1E	EIC EXTINT14	External Interrupt 14
0x1F	EIC EXTINT15	External Interrupt 15
0x20	DMAC CH0	Channel 0
0x21	DMAC CH1	Channel 1
0x22	DMAC CH2	Channel 2
0x23	DMAC CH3	Channel 3
0x24	TCC0 OVF	Overflow
0x25	TCC0 TRG	Trig
0x26	TCC0 CNT	Counter
0x27	TCC0 MC0	Match/Capture 1
0x28	TCC0 MC1	Match/Capture 1
0x29	TCC0 MC2	Match/Capture 2
0x2A	TCC0 MC3	Match/Capture 3
0x2B	TCC1 OVF	Overflow
0x2C	TCC1 TRG	Trig
0x2D	TCC1 CNT	Counter
0x2E	TCC1 MC0	Match/Capture 0
0x2F	TCC1 MC1	Match/Capture 1
0x30	TCC2 OVF	Overflow
0x31	TCC2 TRG	Trig
0x32	TCC2 CNT	Counter
0x33	TCC2 MC0	Match/Capture 0
0x34	TCC2 MC1	Match/Capture 1
0x35	TC0 OVF	Overflow/Underflow
0x36	TC0 MC0	Match/Capture 0
0x37	TC0 MC1	Match/Capture 1
0x38	TC1 OVF	Overflow/Underflow
0x39	TC1 MC0	Match/Capture 0
0x3A	TC1 MC1	Match/Capture 1
0x3B	TC2 OVF	Overflow/Underflow
0x3C	TC2 MC1	Match/Capture 0
0x3D	TC2 MC0	Match/Capture 1
0x3E	TC3 OVF	Overflow/Underflow
0x3F	TC3 MC0	Match/Capture 0
0x40	TC3 MC1	Match/Capture 1
0x41	TC4 OVF	Overflow/Underflow
0x42	TC4 MC0	Match/Capture 0
0x43	TC4 MC1	Match/Capture 1
0x44	ADC0 RESRDY	Result Ready
0x45	ADC0 WINMON	Window Monitor
0x46	ADC1 RESRDY	Result Ready
0x47	ADC1 WINMON	Window Monitor
0x48	AC COMP0	Comparator 0
0x49	AC COMP1	Comparator 1
0x4A	AC COMP2	Comparator 2
0x4B	AC COMP3	Comparator 3
0x4C	AC WIN0	Window 0
0x4D	AC WIN1	Window 1
0x4E	DAC EMPTY	Data Buffer Empty
0x4F	PTC EOC	End of Conversion
0x50	PTC WINCOMP	Window Comparator
0x51	CCL LUTOUT0	CCL output
0x52	CCL LUTOUT1	CCL output
0x53	CCL LUTOUT2	CCL output
0x54	CCL LUTOUT3	CCL output
0x55	PAC ACCERR	Access Error
0x56	-	Reserved
0x57	TC5 OVF	Overflow/Underflow
0x58	TC5 MC0	Match/Capture 0
0x59	TC5 MC1	Match/Capture 1
0x5A	TC6 OVF	Overflow/Underflow
0x5B	TC6 MC0	Match/Capture 0
0x5C	TC6 MC1	Match/Capture 1
0x5D	TC7 OVF	Overflow/Underflow
0x5E	TC7 MC0	Match/Capture 0
0x5F	TC7 MC1	Match/Capture 1
0x60	PDEC_OVF	PDEC Overflow
0x61	PDEC_ERR	PDEC Error
0x62	PDEC_DIR	PDEC Direction
0x63	PDEC_VLC	PDEC VLC
0x64	PDEC_MC0	PDEC MC0
0x65	PDEC_MC1	PDEC MC1
0x66 - 0x7F	Reserved	Reserved

Note:

Refer to the Configuration Summary chapter for the list of peripherals and peripheral instances present in each variant.