5.4 Low Dropout Voltage Regulator (VDD1)

Depending on the product, the VDD1 pin has a nominal voltage output level of 5V or 3.3V, see Product Family.

The voltage regulator needs an external capacitor to compensate for and smooth any disturbances. It is recommended to use an MLC capacitor connected in parallel with a 100 nF ceramic capacitor.

During a short circuit at VDD1, the output current is limited to I_{VDD1_fb_sc}. If the LDO temperature exceeds the T_{OT_sdwn} threshold, the VDD1 output will be switched off. As soon as the junction temperature decreases below T_{OT_release}, the regulator will be switched on again.

Exceeding the maximum sum load current of VDD1 and VDD2 [I_VDD1 + I_VDD2] beyond the output current foldback corner threshold I_{VDD1_fbcorner} leads to a current limitation of LDO1. The current is limited down to the foldback short circuit limit I_{VDD1_fb_sc} with decreasing load resistance. This feature reduces the dissipated power in overloading or short circuit conditions and prevents LDO damage. This principle is illustrated in the Principle Foldback Current Waveform (Figure 5-7).

A proper connection between the exposed pad and a heat sink is recommended to ensure sufficient power dissipation.

If the supply voltage (VS) is below the nominal output voltage of VDD1, the foldback current limitation is disabled and replaced with the standard current limitation (I_VDD1lim).