5.14 Register Summary
(Submit Feedback)| Offset | Name | Bit Pos. | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|
0x00 | Reserved | |||||||||
| 0x01 | DOPMCR | 7:0 | RSTLVL | VDDIOOVSD | Reserved[5:3] | DOPM [2:0] | ||||
| 0x02 | LOPMCR | 7:0 | Reserved[7:2] | LOPM [1:0] | ||||||
| 0x03 | GOPMCR | 7:0 | Reserved[7:3] | GDUOPM [2:0] | ||||||
| 0x04 | WUCR | 7:0 | Reserved[7:2] | LINWUE | LOCWUE | |||||
| 0x05 | GDUCR1 | 7:0 | CCPT [7:2] | CCEN | BEMFEN | |||||
| 0x06 | GDUCR2 | 7:0 | HSOFF | LSOFF | TSWTO [5:4] | EGBLT [3:0] | ||||
| 0x07 | GDUCR3 | 7:0 | ADDTHS [7:6] | ADDTLS [5:4] | HSSRC [3:2] | LSSRC [1:0] | ||||
| 0x08 | GDUCR4 | 7:0 | COMPEN | VDHOVSD | UVVGSEN | UVVGSLVL | VGSUVFLT [3:0] | |||
| 0x09 | ILIMCR | 7:0 | ILIMEN | ILIMFLT [6:3] | ILIMSDEN | Reserved[1:0] | ||||
| 0x0A | ILIMTH | 7:0 | Reserved | DAC [6:0] | ||||||
| 0x0B | SCPCR | 7:0 | SCSDEN | SCFLT [6:3] | SCTHSEL [2:0] | |||||
| 0x0C | CSCR | 7:0 | CSA3EN | CSA2EN | CSA1EN | Reserved | OFFSET [3:2] | GAIN [1:0] | ||
0x0D | Reserved | |||||||||
| 0x0E | MLDCR | 7:0 | Reserved | SOURCE3 | SINK3 | SOURCE2 | SINK2 | SOURCE1 | SINK1 | MLDEN |
| 0x0F | RWPCR | 7:0 | Reserved[7:1] | WP0 | ||||||
| 0x10 | DSR1 | 7:0 | SMTS | VDD2OTPWS | VDD1OTPWS | GDUOTPWS | LOTPWS | GDUS | LTXDOUTS | LTXS |
| 0x11 | DSR2 | 7:0 | Reserved | VDD2OVS | VDD1OVS | VDD2UVS | VDD1UVHS | VDD1UVLS | VGUVS | VCPUVS |
| 0x12 | MLDRR | 7:0 | Reserved[7:6] | DIAG3_HS | DIAG3_LS | DIAG2_HS | DIAG2_LS | DIAG1_HS | DIAG1_LS | |
| 0x13 | SIR1 | 7:0 | VSUPF | WAKE | SYS | ILIM | LDOF | OVTF | VDSSC | VGSUV |
| 0x14 | SIR2 | 7:0 | Reserved | VDD2OV | VDD1OV | VDD2UV | VDD1UVH | VDD1UVL | Reserved[1:0] | |
| 0x15 | SIR3 | 7:0 | VGUV | VCPUV | SCHS3 | SCHS2 | SCHS1 | SCLS3 | SCLS2 | SCLS1 |
| 0x16 | SIR4 | 7:0 | OVTSDVDD2 | OVTSDVDD1 | OVTSDGDU | OVTSDL | OVTPWVDD2 | OVTPWVDD1 | OVTPWGDU | OVTPWL |
| 0x17 | SIR5 | 7:0 | VDHOV | VSUV | LOCWU | LINWU | SPIF | PWRON | SYSERR | OSCF |
| 0x18 | SIECER1 | 7:0 | GSCECE | VDHOVECE | ILIMECE | Reserved[4:3] | VSUVECE | SPIFECE | OVTPWECE | |
| 0x19 | SIECER2 | 7:0 | Reserved[7:5] | VDD2UVECE | VDD1UVHECE | VDD1UVLECE | VDD2OVECE | VDD1OVECE | ||
0x1A ... 0x1F | Reserved | |||||||||
| 0x20 | WDTRIG | 7:0 | WDTRIG [7:0] | |||||||
| 0x21 | WDCR1 | 7:0 | WDC [7:5] | WDPRE [4:3] | WDSLP | WDLW | Reserved | |||
| 0x22 | WDCR2 | 7:0 | WWDP [7:4] | WRPL [3:0] | ||||||
| 0x23 | WDSR | 7:0 | OFF | CACC | ILLCON | TRIGS | OF | OFSLP | ETRIG | Reserved |