5.13 Serial Peripheral Interface (SPI)

The SPI is used to communicate with a host microcontroller. The ATA6847 is configured and operated using SPI transfers. SPI transfers are disabled in Sleep and Deep Sleep modes.

The SPI allows full-duplex data transfer. Status information is returned when new control data are shifted in. The interface also offers read-only access, allowing registers to be read back without changing the register content.

Bit sampling is performed on the falling edge of the clock pin (SCK) and data is shifted in/out on the rising edge (see the figure below).

Figure 5-15. SPI Timing Protocol.

The SPI data is stored in dedicated 8-bit registers, and each register is assigned a unique 7-bit address. Sixteen bits must be transmitted to the device for a single register write operation.

The first byte contain the 7-bit address along with a ‘read/write’ bit (the LSB). The read/write bit must be ‘0’ to indicate a write operation. If this bit is ‘1’, a read operation is performed and any data after this bit is ignored.

The second byte contain the data meant to be written to the register. The contents of the addressed register(s) are returned via the SDO pin, while a read or write operation is performed.

For faster programming, 16, 24 and 32-bit read and write operations are supported. For 24 and 32-bit operations, the register address is automatically incremented: once for a 24-bit operation and twice for a 32-bit operation.

Attempting to write to a non-existing register is not prohibited. If the available address space is exceeded during a write operation, the data beyond the valid address range is ignored without generating an SPI failure event.

Figure 5-16. SPI Transfer Data Structure

The number of transmitted SPI bits is monitored during SPI transfers. If the number of bits is not equal to 16, 24 or 32, the transfer is aborted.

An SPI failure event is captured (SPIF = ‘1’, see SIR1 Register) if the SPI failure detection is enabled (SPIFECE = ‘1’) and at least one of the following SPI failures is detected:

  • SPI clock count error: only 16, 24 and 32-bit commands are valid for both read and write operation
  • Illegal DOPM code (see DOPMCR Register)
  • Attempted write access to locked register

If more than 32 bits are clocked in on the SDI pin during a read and write operation, the data stream on the SDI pin is looped back on the SDO pin from bit 33 onwards.

For the full list of registers, see Register Summary.