4.5.2.2 PHY Timestamping

To ensure that the variable delay is not captured in the timestamp of the LAN8650/1, the MAC does not capture a timestamp based on the time that the Start-of-Frame Delimiter (SFD) crosses the MII interface to the PHY. Instead, it receives a signal from the PHY indicating that the end of the SFD has been transmitted or received on the MDI and uses that to capture the timestamp for all packets when enabled using the SPI protocol. In a busy network, or when using an inexpensive microcontroller, it may not be desirable to timestamp every packet. The LAN8650/1 adds the ability to selectively timestamp on packets that match a desired pattern, such as PTP Sync or other PTP messages.

The pattern matcher will indicate a match for a bit pattern of up to 24 bits at a configured number of nibbles after the SFD. As an example for configuring the pattern matcher, consider the SYNC message format within a MAC frame. As shown above in PTP Message Format, the EtherType field will contain 0x88F7, followed by the transport specific nibble containing 0x1 and a messageType nibble of 0x0. The 24 bit pattern to be matched is then 0x88F710. These will be located immediately after the Destination Address, and Source Address Fields of the Ethernet packet, which means that they are found in nibbles 24 through 29 of the packet. The pattern matcher location is configured as the first nibble after the location of the desired match, so for any gPTP messageType, the location will be 30.

Figure 4-6. PTP Packet Pattern Matching
To configure a match on SYNC message in a transmitted packet:
  • Write the location value of 30 into the Transmit Match Location (TXMLOC) register.
  • Write the top 8 bits of the desired pattern, 0x88, into the Transmit Match Pattern High (TXMPATH) register.
  • Write the bottom 24 bits of the desired pattern, 0xF710, into the Transmit Match Pattern Low (TXMPATL) register,
  • Write all 0’s into the Transmit Match Mask High and Low (TXMMSKH/TXMMSKL) register mask fields so that all 24 bits of the pattern are matched.
    • Setting bits to a '1' will cause the corresponding pattern bit to be ignored during a match. This can be used to allow for multiple messageTypes, for example.
  • Enable the pattern matcher by setting the Transmit Packet Match Enable (TXME) bit in the Transmit Match Control (TXMCTL) register.
  • Request time stamps via the SPI protocol.

Matching receive packets operates in a similar manner, except the receive case uses the Receive Match Location (RXMLOC) register, Receive Match Pattern High (RXMPATH) register, Receive Match Pattern Low (RXMPATL) register, Receive Match Mask High (RXMSKH) Register, Receive Match Mask Low (RXMSKH) register, and Receive Packet Match Enable (RXME) bit in the Receive Match Control (RXMCTL) register.

When the pattern match location is set to zero and the 24-bit pattern match mask is to all 1’s (0xFFFFFF), then every packet will be matched at the SFD and will be timestamped when requested by the SPI protocol. This configuration is not the default configuration of the hardware, but is the default configuration set by all Microchip drivers and in the LAN8650/1 Configuration Application Note, www.microchip.com/DS60001760. When using the packet filter, these register values may be configured as needed.