7.7.6.13 ASRC Interrupt Status Register of Stereo Channel x

The following values are valid for all listed bit names of this register:

0: The corresponding interrupt source is not active.

1: The corresponding interrupt source is active.

Name:	ASRC_ISRx
Offset:	0x98 + x*0x04 [x=0..3]
Reset:	0x00000302
Property:	Read-only


Bit	31	30	29	28	27	26	25	24
		LOCK	FSOUTLOSS	FSINLOSS
Access		R	R	R
Reset		0	0	0


Bit	23	22	21	20	19	18	17	16
							EOMCP	SECE
Access							R	R
Reset							0	0


Bit	15	14	13	12	11	10	9	8
			TXOVR	TXUDR	TXCHUNK	TXFULL	TXEMPTY	TXRDY
Access			R	R	R	R	R	R
Reset			0	0	0	0	1	1


Bit	7	6	5	4	3	2	1	0
			RXOVR	RXUDR	RXCHUNK	RXFULL	RXEMPTY	RXRDY
Access			R	R	R	R	R	R
Reset			0	0	0	0	1	0

Bit 30 – LOCK DPLL Locked Interrupt Status (cleared by writing ASRC_MR.ASRCENx=0)

Bit 29 – FSOUTLOSS Output Sampling Frequency Loss Interrupt Status (cleared on read)

Bit 28 – FSINLOSS Input Sampling Frequency Loss Interrupt Status (cleared on read)

Bit 17 – EOMCP End of Memory Check Period Interrupt Status (cleared on read)

Bit 16 – SECE Security and/or Safety Event Interrupt Status (cleared on read)

Value	Description
0	No security or safety event has occurred since the last read of ASRC_ISR.
1	One or more safety or security events have occurred since the last read of ASRC_ISR. For details on the event, refer to ASRC_WPSR and ASRC_ESR direct access related error reports.

Bit 13 – TXOVR Transmit Over Flow Interrupt Status (cleared on read)

Bit 12 – TXUDR Transmit Under Flow Interrupt Status (cleared on read)

Bit 11 – TXCHUNK Transmit FIFO Chunk Interrupt Status (cleared automatically when the input FIFO has fewer samples than configured in ASRC_CH_CONF.CHUNKx)

Bit 10 – TXFULL Transmit FIFO Full Interrupt Status (cleared automatically when ASRC starts converting data)

Bit 9 – TXEMPTY Transmit FIFO Empty Interrupt Status (cleared when writing in ASRC_THRx)

Bit 8 – TXRDY Transmit Ready Interrupt Status (cleared automatically when input FIFO is full)

Bit 5 – RXOVR Receive Over Flow Interrupt Status (cleared on read)

Bit 4 – RXUDR Receive Under Flow Interrupt Status (cleared on read)

Bit 3 – RXCHUNK Receive FIFO Chunk Interrupt Status (cleared automatically when the output FIFO has fewer samples than configured in ASRC_CH_CONF.CHUNKx)

Bit 2 – RXFULL Receive FIFO Full Interrupt Status (cleared by reading ASRC_RHRx)

Bit 1 – RXEMPTY Receive FIFO Empty Interrupt Status (cleared automatically when ASRC has converted one sample)

Bit 0 – RXRDY Receive Ready Interrupt Status (cleared automatically when ASRC has converted one sample)

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