7.7.6.17 ASRC Direct Access Peripheral Selection Register
This register can only be written if the WPEN bit is cleared in ASRC_WPMR.
Note:
- The Direct Access mode related configurations (ASRC_DAPSELR.IN_CHx/OUT_CHx) must be programmed prior to enabling the channels in ASRC_MR.ASRCENx.
- It is not possible to directly transfer data from one audio peripheral to more than one direct access channels. When several IN_CHx carry the same value whereas more than one direct access transmit channel are enabled (ASRC_MR.DATHRx=1), an error is reported in ASRC_ESR.DAPSELIREDERR. It is not possible to directly transfer data from more than one direct access channel to one audio peripheral. When several OUT_CHx carry the same value whereas more than one direct access receive channel are enabled (ASRC_MR.DARHRx=1), an error is reported in ASRC_ESR.DAPSELOREDERR.
- An error is reported in ASRC_ESR.DAPSELIMAXERR when the value configured in IN_CHx overpasses the maximum number of audio peripherals available for the direct transmit related channel. An error is reported in ASRC_ESR.DAPSELOMAXERR when the value configured in OUT_CHx overpasses the maximum number of audio peripherals available for the direct receive related channel. The related channel must be enabled to report an error.
| Name: | ASRC_DAPSELR |
| Offset: | 0xB4 |
| Reset: | 0x32103210 |
| Property: | Read/Write |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| OUT_CH3[2:0] | OUT_CH2[2:0] | ||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | |||
| Reset | 0 | 1 | 1 | 0 | 1 | 0 | |||
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| OUT_CH1[2:0] | OUT_CH0[2:0] | ||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | |||
| Reset | 0 | 0 | 1 | 0 | 0 | 0 | |||
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| IN_CH3[2:0] | IN_CH2[2:0] | ||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | |||
| Reset | 0 | 1 | 1 | 0 | 1 | 0 | |||
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| IN_CH1[2:0] | IN_CH0[2:0] | ||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | |||
| Reset | 0 | 0 | 1 | 0 | 0 | 0 | |||
Bits 16:18, 20:22, 24:26, 28:30 – OUT_CHx Direct Access Channel x Output Audio Peripheral Source
| Value | Name | Description |
|---|---|---|
| 0 | AUDIOSTREAM0 | The direct access channel x is directly driving the I2SMCC1 TX when ASRC_MR.DARHRx=1 or ASRC_MR.DARHRM=1. |
| 1 | AUDIOSTREAM1 | The direct access channel x is directly driving the I2SMCC0 TX when ASRC_MR.DARHRx=1 or ASRC_MR.DARHRM=1. |
| 2 | AUDIOSTREAM2 | The direct access channel x is directly driving the SPDIFTX when ASRC_MR.DARHRx=1 or ASRC_MR.DARHRM=1. |
| 3 | AUDIOSTREAM3 | The direct access channel x is directly driving the SSC0 TX when ASRC_MR.DARHRx=1 or ASRC_MR.DARHRM=1. |
| 4 | AUDIOSTREAM4 | The direct access channel x is directly driving the SSC1 TX when ASRC_MR.DARHRx=1 or ASRC_MR.DARHRM=1. |
Bits 0:2, 4:6, 8:10, 12:14 – IN_CHx Direct Access Channel x Input Audio Peripheral Source
| Value | Name | Description |
|---|---|---|
| 0 | AUDIOSTREAM0 | The direct access channel x is directly driven by I2SMCC0 RX when ASRC_MR.DATHRx=1or ASRC_MR.DATHRM=1. |
| 1 | AUDIOSTREAM1 | The direct access channel x is directly driven by I2SMCC1 RX when ASRC_MR.DATHRx=1or ASRC_MR.DATHRM=1. |
| 2 | AUDIOSTREAM2 | The direct access channel x is directly driven by SPDIFRX when ASRC_MR.DATHRx=1or ASRC_MR.DATHRM=1. |
| 3 | AUDIOSTREAM3 | The direct access channel x is directly driven by PDMC0 when ASRC_MR.DATHRx=1or ASRC_MR.DATHRM=1. |
| 4 | AUDIOSTREAM4 | The direct access channel x is directly driven by PDMC1 when ASRC_MR.DATHRx=1or ASRC_MR.DATHRM=1. |
| 5 | AUDIOSTREAM5 | The direct access channel x is directly driven by SSC0 RX when ASRC_MR.DATHRx=1or ASRC_MR.DATHRM=1. |
| 6 | AUDIOSTREAM6 | The direct access channel x is directly driven by SSC1 RX. when ASRC_MR.DATHRx=1 or ASRC_MR.DATHRM=1. |