7.7.6.16 ASRC Fault Injection Register
This register can only be written if the FIRDIS bit is cleared.
All bits are write-only. FIRDIS is write-once.
| Name: | ASRC_FIR |
| Offset: | 0xB0 |
| Reset: | 0x00000000 |
| Property: | Write-only |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| FIKEY[23:16] | |||||||||
| Access | W | W | W | W | W | W | W | W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| FIKEY[15:8] | |||||||||
| Access | W | W | W | W | W | W | W | W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| FIKEY[7:0] | |||||||||
| Access | W | W | W | W | W | W | W | W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| FIRDIS | FPARE | F3 | F2 | F1 | F0 | ||||
| Access | W | W | W | W | W | W | |||
| Reset | 0 | 0 | 0 | 0 | 0 | 0 |
Bits 31:8 – FIKEY[23:0] Fault Injection Access Key
| Value | Name | Description |
|---|---|---|
| 0x414649 | PASSWD | Writing any other value in this field aborts the write operation. |
Bit 7 – FIRDIS Fault Injection Register Disable
| Value | Name | Description |
|---|---|---|
| 0 | NO_EFFECT | No effect |
| 1 | ACTIVE | Disables the fault injection until the next hardware reset. The command is valid only if the ASRCC_WPSR.SEQE=0 and the other bits are cleared (F0=F1=F2=F3=FPARE=0). |
Bit 5 – FPARE Single Fault for ASRC Mode Register
| Value | Name | Description |
|---|---|---|
| 0 | NO_EFFECT | No effect |
| 1 | INJECT_CLEAR | Injects a single fault on the configuration register if the ASRC DSPs are all disabled (for security reason), the flag ASRC_WPSR.SEQE=1 and the flag ASRC_ISRx.SECE =1. Clears the fault if it has been previously injected. |
Bit 3 – F3 Single Fault for ASRC Write Protection Control Enable (ASRC_WPMR.WPCREN)
| Value | Description |
|---|---|
| 0 | Clears the fault. |
| 1 | Injects a single fault on the reinforced safety for the ASRC_WPMR.WPCREN bit if 0x414649 (“AFI” in ASCII) is written in the FIKEY field at the same time. The ASRC remains in the same state, the flag ASRC_ISRx.SECE=1 and the flag ASRC_WPSR.SDEE=1. |
Bit 2 – F2 Single Fault for ASRC Write Protection Interrupt Enable (ASRC_WPMR.WPITEN)
| Value | Description |
|---|---|
| 0 | Clears the fault. |
| 1 | Injects a single fault on the reinforced safety for the ASRC_WPMR.WPITEN bit if 0x414649 (“AFI” in ASCII) is written in the FIKEY field at the same time. The ASRC remains in the same state, the flag ASRC_ISRx.SECE=1 and the flag ASRC_WPSR.SDEE=1. |
Bit 1 – F1 Single Fault for ASRC Write Protection Configuration Enable (ASRC_WPMR.WPEN)
| Value | Description |
|---|---|
| 0 | Clears the fault. |
| 1 | Injects a single fault on the reinforced safety for the ASRC_WPMR.WPEN bit if 0x414649 (“AFI” in ASCII) is written in the FIKEY field at the same time. The ASRC remains in the same state, the flag ASRC_ISRx.SECE=1 and the flag ASRC_WPSR.SDEE=1. |
Bit 0 – F0 Single Fault for ASRC DSP0 Enable (ASRC_MR.ASRCEN)
| Value | Description |
|---|---|
| 0 | Clears the fault. Writing a 0 to this bit clears ASRC_ESR.ROMS/SRAMS if the write is done before reading ASRC_WPSR and before starting a new memory check procedure. |
| 1 | Injects a single fault on the reinforced safety for the ASRC_MR.ASRCENx bit if 0x414649 (“AFI” in ASCII) is written in the FIKEY field at the same time. The ASRC remains in the same state, the flag ASRC_ISRx.SECE=1 and the flag ASRC_WPSR.SDEE=1. When the memory check is started (ASRC_CR.MEMCHECK=1), injects also a fault in the data read from embedded memories to verify the memory checker. Thus at the end of the memory check period (ASRC_ISRx.EOMCP=1) the flag ASRC_ESR.ROMS=1 and ASRC_ESR.SRAMS=1. |