7.7.6.19 ASRC Status Register
| Name: | ASRC_SR |
| Offset: | 0xBC |
| Reset: | 0x02020202 |
| Property: | Read-only |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| FSOUTERR3 | FSINERR3 | DPLL3 | FIFOEMPTY3 | FIFOFULL3 | |||||
| Access | R | R | R | R | R | ||||
| Reset | 0 | 0 | 0 | 1 | 0 |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| FSOUTERR2 | FSINERR2 | DPLL2 | FIFOEMPTY2 | FIFOFULL2 | |||||
| Access | R | R | R | R | R | ||||
| Reset | 0 | 0 | 0 | 1 | 0 |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| FSOUTERR1 | FSINERR1 | DPLL1 | FIFOEMPTY1 | FIFOFULL1 | |||||
| Access | R | R | R | R | R | ||||
| Reset | 0 | 0 | 0 | 1 | 0 |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| FSOUTERR0 | FSINERR0 | DPLL0 | FIFOEMPTY0 | FIFOFULL0 | |||||
| Access | R | R | R | R | R | ||||
| Reset | 0 | 0 | 0 | 1 | 0 |
Bits 4, 12, 20, 28 – FSOUTERRx DSPx Output Sampling Frequency Status
| Value | Description |
|---|---|
| 0 | DSPx output sampling frequency is correct. |
| 1 | DSPx output sampling frequency is abnormal (loss or deviation greater than four times the initial value registered when the conversion has been enabled). |
Bits 3, 11, 19, 27 – FSINERRx DSPx Input Sampling Frequency Status
| Value | Description |
|---|---|
| 0 | DSPx input sampling frequency is correct. |
| 1 | DSPx input sampling frequency is abnormal (loss or deviation greater than four times the initial value registered when the conversion has been enabled). |
Bits 2, 10, 18, 26 – DPLLx DSPx Digital PLL Status
| Value | Name | Description |
|---|---|---|
| 0 | UNLOCKED | DSPx Digital PLL is unlocked. |
| 1 | LOCKED | DSPx Digital PLL is locked. |
Bits 1, 9, 17, 25 – FIFOEMPTYx DSPx FIFO Empty
| Value | Description |
|---|---|
| 0 | DSPx FIFO is not empty. |
| 1 | DSPx FIFO is empty. |
Bits 0, 8, 16, 24 – FIFOFULLx DSPx FIFO Full
| Value | Description |
|---|---|
| 0 | DSPx FIFO is not full. |
| 1 | DSPx FIFO is full. |