7.7.6.21 ASRC Write Protection Status Register
| Name: | ASRC_WPSR |
| Offset: | 0xE8 |
| Reset: | 0x00000000 |
| Property: | Read/Write |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| SWETYP[1:0] | |||||||||
| Access | R/W | R/W | |||||||
| Reset | 0 | 0 | |||||||
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| WPSRC[15:8] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| WPSRC[7:0] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| SDEE | SWE | SEQE | CFGERR | WPVS | |||||
| Access | R/W | R/W | R/W | R/W | R/W | ||||
| Reset | 0 | 0 | 0 | 0 | 0 |
Bits 25:24 – SWETYP[1:0] Software Error Type (cleared on read)
| Value | Name | Description |
|---|---|---|
| 0 | READ_WO | A Write-only register has been read. |
| 1 | WRITE_RO | A write access has been performed on a Read-only register. |
| 2 | UNDEF_RW | Access to an undefined address. |
| 3 | – | Reserved |
Bits 23:8 – WPSRC[15:0] Write Protection Source (cleared on read)
If a write protection violation has occurred (WPVS=1), this field reports the address of the last violation.
Bit 4 – SDEE Single or Dual Event Error (cleared by reconfiguring the faulty registers or by clearing the error via ASRC_FIR)
| Value | Description |
|---|---|
| 0 | No single or dual error detected in ASRC_MR.ASRCENx, ASRC_WPMR.WPEN/WPITEN/WPCREN bits. When testing the ability for SDEE to rise by introducing a fault via ASRC_FIR, the clear is performed by first clearing the fault via ASRC_FIR, then reading ASRC_WPSR again. |
| 1 | Single or dual error detected in ASRC_MR.ASRCENx, ASRC_WPMR.WPEN/WPITEN/WPCREN bits. If a single error event occurred, the error is filtered and has no effect on ASRC. |
Bit 3 – SWE Software Control Error (cleared on read)
| Value | Description |
|---|---|
| 0 |
No software error has occurred since the last read of ASRC_WPSR. |
| 1 |
A software error has occurred since the last read of ASRC_WPSR. The field SWETYP details the type of software error; the associated incorrect software access is reported in the field WPVSRC (if WPVS=0). |
Bit 2 – SEQE Internal Sequencer Error (cleared on read)
| Value | Description |
|---|---|
| 0 | No peripheral internal sequencer error has occurred since the last read of ASRC_WPSR |
| 1 | A peripheral internal sequencer error has occurred since the last read of ASRC_WPSR. This flag is set under abnormal operating conditions or if the fault injection ASRC_FIR.FPARE is performed (only available if ASRC DSPs are all disabled). All ASRC configuration registers are monitored with a parity check for each register. |
Bit 1 – CFGERR SRC Configuration Error (cleared by correcting the faulty configuration)
| Value | Description |
|---|---|
| 0 | No configuration error is reported in ASRC_ESR since the last read of ASRC_WPSR. |
| 1 | A configuration error has been detected and reported in ASRC_ESR, since the last read of ASRC_WPSR. |
Bit 0 – WPVS Write Protection Violation Status (cleared on read)
| Value | Description |
|---|---|
| 0 | No write protection violation has occurred since the last read of ASRC_WPSR |
| 1 | A write protection violation has occurred since the last read of ASRC_WPSR. If this violation is an unauthorized attempt to write a protected register, the associated violation is reported in field WPSRC. |