7.7.6.1 ASRC Control Register
This register can only be written if the WPCREN bit is cleared in ASRC_WPMR.
| Name: | ASRC_CR |
| Offset: | 0x00 |
| Reset: | – |
| Property: | Write-only |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| Access | |||||||||
| Reset |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| Access | |||||||||
| Reset |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| DSPMEMSEL[1:0] | MEMCHECK | SWRST | |||||||
| Access | W | W | W | W | |||||
| Reset | – | – | – | – | |||||
Bits 3:2 – DSPMEMSEL[1:0] DSP Memory Selection
| Value | Name | Description |
|---|---|---|
| 0 | ALL_DSP_MEM |
Memories of all DSPs are checked when MEMCHECK=1. When the flag ASRC_ESR.SRAMS=1, one error has been detected in one of the memories. To determine which DSP is affected, the memory check procedure must be restarted with DSPMEMSEL > 0. Note: When using only DSP0 or DSP1 or DSP3, it is possible
to start the check procedure only for the selected DSP. The check of DSP2
memories requires several steps.
|
| 1 | DSP0_MEM | Only memories of DSP0 are checked when MEMCHECK=1. When the flag ASRC_ESR.SRAMS=1, one error has been detected in one of the memories associated to DSP0. The errors that may be located in other DSP memories does not impact the report on ASRC_ESR.SRAMS=1. |
| 2 | DSP1_MEM | Only memories of DSP1 are checked when MEMCHECK=1. When the flag ASRC_ESR.SRAMS=1, one error has been detected in one of the memories associated to DSP1. The errors that may be located in other DSP memories does not impact the report on ASRC_ESR.SRAMS=1. |
| 3 | DSP3_MEM | Only memories of DSP3 are checked when MEMCHECK=1. When the flag ASRC_ESR.SRAMS=1, one error has been detected in one of the memories associated to DSP3. The errors that may be located in other DSP memories does not impact the report on ASRC_ESR.SRAMS=1. |
Bit 1 – MEMCHECK Embedded Memory Check
| Value | Description |
|---|---|
| 0 | No effect |
| 1 | Starts a memory check when the DSPs are all disabled (ASRC_MR.ASRCENx=0). The end of the verification period is provided in ASRC_ISRx.EOMCP and the status is available in ASRC_ESR.ROMS/SRAMS at the end of the verification period. Clears the ASRC_ESR.ROMS/SRAMS flags. |
Bit 0 – SWRST Software Reset
| Value | Description |
|---|---|
| 0 | No effect |
| 1 | Resets the ASRC. |