31.1.12.1 Page Erase Sequence

A page erase performs an erase of a single page of PFM or BFM, or select pages in CFM (User, Boot), as long as it is not write protected. . The page to be erased is selected using ADDR. The lower bits of the address given by ADDR are ignored in page selection.

Note:

1) During the page erase, accessing any uncached/unbuffered address within the panel containing the page causes that access to stall until the erase finishes. It is user code responsibility to prevent or handle that situation.

2) It is also the responsibility of the programmer's code to ensure that no bus initiators, including the CPU, access the Flash region, the entire PFM of the panel, or the entire Boot of the panel, that is to be - or is being - erased.

Page Erase

A Page Erase sequence comprises the following steps:

  1. <Desired NVMOP> is Page Erase.
  2. Follow the Start Sequencer from Start Sequencer.
  3. Wait for NVM Interrupt from Interrupts.
  4. Check the INTFLAG bits to ensure that the program sequence completed successfully, and then clear all bits in INTFLAG. See Errors and Flags about error flags.

A page of Flash can be erased if its associated page write protection is not enabled, see Debug Access Level.

Page Erase Timing

Page Erase timing is dominated by setup (Tnvs), erase time (Terase) and recovery (Trcv) delays. Using the timing shown in Non-Volatile Memory Controller (NVM) Electrical Specifications, the total time to erase one page is:

Time to Erase Page = Tnvs + Terase+ Trcv+ Trw

Page Erase Retry

Erase Retry is not longer needed to achieve 20K cycle endurance, use Pre-Program for 20K.