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15.6.10 Error Capture Syndrome Register
Table 15-11. Register Bit Attribute
Legend Symbol Description Symbol Description Symbol Description R Readable bit HC Cleared by Hardware (Grey cell) Unimplemented W Writable bit HS Set by Hardware X Bit is unknown at Reset K Write to clear S Software settable bit — —
Name: MCRAMC_ERRCSYN Offset: 0x28 Reset: 0x00000000 Property: R
Bit 31 30 29 28 27 26 25 24 Access Reset
Bit 23 22 21 20 19 18 17 16 Access Reset
Bit 15 14 13 12 11 10 9 8 ERR2 ERR1 Access R R Reset 0 0
Bit 7 6 5 4 3 2 1 0 ERCSYN[7:0] Access R R R R R R R R Reset 0 0 0 0 0 0 0 0
Bit 15 – ERR2 ECC Double Bit Error Value Name Description 0 Not a Double bit error. 1 Double bit error.
Bit 14 – ERR1 ECC Single Bit Error
Bits 7:0 – ERCSYN[7:0] ECC SECDED Error Capture Syndrome Value Name Description 0 Not a Single bit error. 1 Single bit error.
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