33.14.14 Pin Configuration

There are up to 32 Pin Configuration registers in each PORT group, one for each I/O line.

Table 33-24. Peripheral Port Mux Control Mapping
Port PINCFGn.MUXEN Value	Port WRCONFIG.PMUX Value	Peripheral Function	Description
0	N/A	Port	Normal Port in /out functions (Pxy)
1	00	EIC / EIC_EXTINT(n)	External Interrupts
1	01	ADC / CMP	ADC and Analog Comparator
1	03	SERCOM(n)	SERCOMn (UART, I²C, SPI)
1	04	EBI	External Bus Interface
1	05	TCC WO(n)	Timer/Counter Controller
1	06	MLB	Media Local Bus
1	07	CAN(n) / SQI(n)	CAN, Serial Quad Interface
1	08	SDMMC	SD/MMC Host Controller (Memory Card Interface)
1	09	I2S / SWCLK, SWDIO, SWO, TRACE_CLK, TRACE_DATA[3:0]	I²S audio and, Debug and debug Trace
1	0A	ETH	Ethernet
1	0B	Only 2 alternate ETH signals	RX_CLK on PD12 and GTX_CLK on PD05
1	0C	GCLK	Controls GCLK_IO[7:2]
1	0F	PTC	Peripheral Touch Controller

Note: All undefined values of WRCONFIG.PMUX are reserved.

Table 33-25. Port Pin Configuration Register Mapping
Port Group	Packages
Port Group	100 pin TQFP EP	144 pin TQFP EP	144 pin TFBGA	176 pin TFBGA	208 pin TFBGA
PORT A (GROUP 0)	PA[0:20]	PA[0:29]	PA[0:29}	PA[0-31]	PA[0-31]
PINCFGn Registers	n=[0-20]	n=[0-29]	n=[0-29]	n=[0-31]	n=[0-31]
PINCFGn.SLEWLIM (Only Exists On:)	n=(0-4)	n=(0-4, 21)	n=(0-4, 21)	n=(0-4, 21, 30, 31)	n=(0-4, 21, 30, 31)
PORT B (GROUP 1)	PB[0:17]	PB[0:26]	PB[0:26]	PB[0:31]	PB[0:31]
PINCFGn Registers	n=[0-17]	n=[0-26]	n=[0-26]	n=[0-31]	n=[0-31]
PINCFGn.SLEWLIM (Only Exists On:)	n=(0-4)	n=(0-4, 21)	n=(0-4, 21)	n=(0-4, 21, 30, 31)	n=(0-4, 21, 30, 31)
PORT C (GROUP 2)	PC[0:15]	PC[0:29]	PC[0:29]	PC[0:31]	PC[0:31]
PINCFGn Registers	n=[0-15]	n=[0-29]	n=[0-29]	n=[0-31]	n=[0-31]
PINCFGn.SLEWLIM (Only Exists On:)	n=(0-4)	n=(0-4, 21)	n=(0-4, 21)	n=(0-4, 21, 30, 31)	n=(0-4, 21, 30, 31)
PORT D (GROUP 3)	PD[0:12]	PD[0:21]	PD[0:21]	PD[0:23]	PD[0:29]
PINCFGn Registers	n=[0-15]	n=[0-29]	n=[0-29]	n=[0-31]	n=[0-31]
PINCFGn.SLEWLIM (Only Exists On:)	n=(0-4)	n=(0-4, 21)	n=(0-4, 21)	n=(0-4, 21, 30, 31)	n=(0-4, 21, 30, 31)
PORT E (GROUP 4)	----	----	----	PE[0:3]	PE[0:11]
PINCFGn Registers	----	----	----	n=[0-3]	n=[0-11]
PINCFGn.SLEWLIM (Only Exists On:)	----	----	----	n=(0-3)	n=(0-4)
PORT F (GROUP 5)	----	----	----	PF[5]	PF[0:8]
PINCFGn Registers	----	----	----	n=[5]	n=[0-8]
PINCFGn.SLEWLIM (Only Exists On:)	----	----	----	----	n=(0-4)
PORT G (GROUP 6)	----	----	----	PG[0-3]	PG[0-11]
PINCFGn Registers	----	----	----	n=[0-3]	n=[0-11]
PINCFGn.SLEWLIM (Only Exists On:)	----	----	----	n=(0-3)	n=(0-4)

EXAMPLE:

PORT_REGS->GROUP[2].PORT_PINCFG4 = 0x12; /* I/O pin PC4, Slew rate control enabled (4x slower), input buffer enabled */

Table 33-26. Register Bit Attribute Legend
Symbol	Description	Symbol	Description	Symbol	Description
R	Readable bit	HC	Cleared by Hardware	(Grey cell)	Unimplemented
W	Writable bit	HS	Set by Hardware	X	Bit is unknown at Reset
K	Write to clear	S	Software settable bit	—	—

Name:	PINCFG
Offset:	0x40 + n*0x01 [n=0..31]
Reset:	0x00
Property:	RW


Bit	7	6	5	4	3	2	1	0
	DRVSTR[1:0]		SLEWLIM[1:0]		ODRAIN	PULLEN	INEN	PMUXEN
Access	RW	RW	RW	RW	RW	RW	RW	RW
Reset	0	0	0	0	0	0	0	0

Bits 7:6 – DRVSTR[1:0] Output Driver Strength Selection

Bits 5:4 – SLEWLIM[1:0] Output Driver Slew Rate Selection

Note:

Only some pins have output TRISE/TFALL slew limit control. See Table: _____ Port Pin Configuration Register Mapping below for details.
Slew rate control can be used to improve signal integrity for high speed signals if improper external HDW resistor termination was not utilized.
If an I²C function is enabled on a pin, the corresponding PINCFGn.SLEWLIM MUST = 0x00.

Value	Name	Description
0x0	FAST	Slew rate control disabled (fast rise/fall time operation)
0x1	SLOW4	Slew rate control enabled (4x slower)
0x2	SLOW8	Slew rate control enabled (8x slower)
0x3	SLOW12	Slew rate control enabled (12x slower)

Bit 3 – ODRAIN Open Drain Output

Value	Description
0	The open drain output is disabled.
1	The open drain output is enabled.

Bit 2 – PULLEN Pull Enable

This bit enables the internal pull-up or pull-down resistor of an I/O pin configured as an input.

Value	Description
0	Internal pull resistor is disabled and the input is in a high-impedance configuration.
1	Internal pull resistor is enabled and the input is driven to a defined logic level in the absence of external input.

Bit 1 – INEN Input Enable

This bit controls the input buffer of an I/O pin configured as either an input or output.

Writing a zero to this bit disables the input buffer completely, preventing read-back of the Physical Pin state when the pin is configured as either an input or output.

Value	Description
0	Input buffer for the I/O pin is disabled and the input value will not be sampled.
1	Input buffer for the I/O pin is enabled and the input value will be sampled when required.

Bit 0 – PMUXEN Peripheral Multiplexer Enable

This bit enables or disables the peripheral multiplexer selection set in the Peripheral Multiplexing register (PMUXm, m=0,...15) to enable or disable alternative peripheral control over an I/O pin direction and output drive value.

Writing a zero to this bit allows the PORT to control the pad direction via the Data Direction register (DIR) and output logic level via the Data Output Value register (OUT). The peripheral multiplexer value in PMUXm is ignored. Writing '1' to this bit enables the peripheral selection in PMUXm to control the pad. In this configuration, the Physical Pin state may still be read from the Data Input Value register (IN) if PINCFGn.INEN is set.

Value	Description
0	The peripheral multiplexer selection is disabled and the PORT registers control the direction and output drive value.
1	The peripheral multiplexer selection is enabled and the selected peripheral function controls the direction and output drive value.