33.14.9 Data Input Value

There are up to 32 Pin Configuration registers in each PORT group, one for each I/O line.

Table 33-14. Peripheral Port Mux Control Mapping
Port PINCFGn.MUXEN Value	Port WRCONFIG.PMUX Value	Peripheral Function	Description
0	N/A	Port	Normal Port in /out functions (Pxy)
1	00	EIC / EIC_EXTINT(n)	External Interrupts
1	01	ADC / CMP	ADC and Analog Comparator
1	03	SERCOM(n)	SERCOMn (UART, I²C, SPI)
1	04	EBI	External Bus Interface
1	05	TCC WO(n)	Timer/Counter Controller
1	06	MLB	Media Local Bus
1	07	CAN(n) / SQI(n)	CAN, Serial Quad Interface
1	08	SDMMC	SD/MMC Host Controller (Memory Card Interface)
1	09	I2S / SWCLK, SWDIO, SWO, TRACE_CLK, TRACE_DATA[3:0]	I²S audio and, Debug and debug Trace
1	0A	ETH	Ethernet
1	0B	Only 2 alternate ETH signals	RX_CLK on PD12 and GTX_CLK on PD05
1	0C	GCLK	Controls GCLK_IO[7:2]
1	0F	PTC	Peripheral Touch Controller

Note: All undefined values of WRCONFIG.PMUX are reserved.

Table 33-15. Port Pin Configuration Register Mapping
Port Group	Packages
Port Group	100 pin TQFP EP	144 pin TQFP EP	144 pin TFBGA	176 pin TFBGA	208 pin TFBGA
PORT A (GROUP 0)	PA[0:20]	PA[0:29]	PA[0:29}	PA[0-31]	PA[0-31]
PINCFGn Registers	n=[0-20]	n=[0-29]	n=[0-29]	n=[0-31]	n=[0-31]
PINCFGn.SLEWLIM (Only Exists On:)	n=(0-4)	n=(0-4, 21)	n=(0-4, 21)	n=(0-4, 21, 30, 31)	n=(0-4, 21, 30, 31)
PORT B (GROUP 1)	PB[0:17]	PB[0:26]	PB[0:26]	PB[0:31]	PB[0:31]
PINCFGn Registers	n=[0-17]	n=[0-26]	n=[0-26]	n=[0-31]	n=[0-31]
PINCFGn.SLEWLIM (Only Exists On:)	n=(0-4)	n=(0-4, 21)	n=(0-4, 21)	n=(0-4, 21, 30, 31)	n=(0-4, 21, 30, 31)
PORT C (GROUP 2)	PC[0:15]	PC[0:29]	PC[0:29]	PC[0:31]	PC[0:31]
PINCFGn Registers	n=[0-15]	n=[0-29]	n=[0-29]	n=[0-31]	n=[0-31]
PINCFGn.SLEWLIM (Only Exists On:)	n=(0-4)	n=(0-4, 21)	n=(0-4, 21)	n=(0-4, 21, 30, 31)	n=(0-4, 21, 30, 31)
PORT D (GROUP 3)	PD[0:12]	PD[0:21]	PD[0:21]	PD[0:23]	PD[0:29]
PINCFGn Registers	n=[0-15]	n=[0-29]	n=[0-29]	n=[0-31]	n=[0-31]
PINCFGn.SLEWLIM (Only Exists On:)	n=(0-4)	n=(0-4, 21)	n=(0-4, 21)	n=(0-4, 21, 30, 31)	n=(0-4, 21, 30, 31)
PORT E (GROUP 4)	----	----	----	PE[0:3]	PE[0:11]
PINCFGn Registers	----	----	----	n=[0-3]	n=[0-11]
PINCFGn.SLEWLIM (Only Exists On:)	----	----	----	n=(0-3)	n=(0-4)
PORT F (GROUP 5)	----	----	----	PF[5]	PF[0:8]
PINCFGn Registers	----	----	----	n=[5]	n=[0-8]
PINCFGn.SLEWLIM (Only Exists On:)	----	----	----	----	n=(0-4)
PORT G (GROUP 6)	----	----	----	PG[0-3]	PG[0-11]
PINCFGn Registers	----	----	----	n=[0-3]	n=[0-11]
PINCFGn.SLEWLIM (Only Exists On:)	----	----	----	n=(0-3)	n=(0-4)

EXAMPLE:

PORT_REGS->GROUP[2].PORT_PINCFG4 = 0x12; /* I/O pin PC4, Slew rate control enabled (4x slower), input buffer enabled */

Table 33-16. Register Bit Attribute Legend
Symbol	Description	Symbol	Description	Symbol	Description
R	Readable bit	HC	Cleared by Hardware	(Grey cell)	Unimplemented
W	Writable bit	HS	Set by Hardware	X	Bit is unknown at Reset
K	Write to clear	S	Software settable bit	—	—

Bits 31:0 – IN[31:0] PORT Data Input Value