This register allows the user to toggle the drive level of one or more
output I/O pins, without doing a read-modify-write operation. Changes in this
register will also be reflected in the Data Output Value (OUT), Data Output Value
Set (OUTSET), and Data Output Value Clear (OUTCLR) registers.
Table 33-10. Register Bit Attribute
Legend
Symbol
Description
Symbol
Description
Symbol
Description
R
Readable bit
HC
Cleared by Hardware
(Grey cell)
Unimplemented
W
Writable bit
HS
Set by Hardware
X
Bit is unknown at Reset
K
Write to clear
S
Software settable bit
—
—
Name:
OUT
Offset:
0x10
Reset:
0x00000000
Property:
RW
Bit
31
30
29
28
27
26
25
24
OUT[31:24]
Access
RW
RW
RW
RW
RW
RW
RW
RW
Reset
0
0
0
0
0
0
0
0
Bit
23
22
21
20
19
18
17
16
OUT[23:16]
Access
RW
RW
RW
RW
RW
RW
RW
RW
Reset
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
OUT[15:8]
Access
RW
RW
RW
RW
RW
RW
RW
RW
Reset
0
0
0
0
0
0
0
0
Bit
7
6
5
4
3
2
1
0
OUT[7:0]
Access
RW
RW
RW
RW
RW
RW
RW
RW
Reset
0
0
0
0
0
0
0
0
Bits 31:0 – OUT[31:0] PORT Data Output Value
The online versions of the documents are provided as a courtesy. Verify all content and data in the device’s PDF documentation found on the device product page.