33.14.12 Event Input Control

There are up to four input event pins for each PORT group. Each byte of this register addresses one Event input pin.

Table 33-19. Register Bit Attribute Legend
Symbol	Description	Symbol	Description	Symbol	Description
R	Readable bit	HC	Cleared by Hardware	(Grey cell)	Unimplemented
W	Writable bit	HS	Set by Hardware	X	Bit is unknown at Reset
K	Write to clear	S	Software settable bit	—	—

Name:	EVCTRL
Offset:	0x2C
Reset:	0x00000000
Property:	RW


Bit	31	30	29	28	27	26	25	24
	PORTEI3	EVACT3[1:0]		PID3[4:0]
Access	RW	RW	RW	RW	RW	RW	RW	RW
Reset	0	0	0	0	0	0	0	0


Bit	23	22	21	20	19	18	17	16
	PORTEI2	EVACT2[1:0]		PID2[4:0]
Access	RW	RW	RW	RW	RW	RW	RW	RW
Reset	0	0	0	0	0	0	0	0


Bit	15	14	13	12	11	10	9	8
	PORTEI1	EVACT1[1:0]		PID1[4:0]
Access	RW	RW	RW	RW	RW	RW	RW	RW
Reset	0	0	0	0	0	0	0	0


Bit	7	6	5	4	3	2	1	0
	PORTEI0	EVACT0[1:0]		PID0[4:0]
Access	RW	RW	RW	RW	RW	RW	RW	RW
Reset	0	0	0	0	0	0	0	0

Bit 31 – PORTEI3 PORT Event Input Enable 3

Bits 30:29 – EVACT3[1:0] PORT Event Action 3

Bits 28:24 – PID3[4:0] PORT Event Pin Identifier 3

Bit 23 – PORTEI2 PORT Event Input Enable 2

Bits 22:21 – EVACT2[1:0] PORT Event Action 2

Bits 20:16 – PID2[4:0] PORT Event Pin Identifier 2

Bit 15 – PORTEI1 PORT Event Input Enable 1

Bits 14:13 – EVACT1[1:0] PORT Event Action 1

Bits 12:8 – PID1[4:0] PORT Event Pin Identifier 1

Bit 7 – PORTEI0 PORT Event Input Enable 0

Bits 6:5 – EVACT0[1:0] PORT Event Action 0

Value	Name	Description
0x0	OUT	Event output to pin
0x1	SET	Set output register of pin on event
0x2	CLR	Clear output register of pin on event
0x3	TGL	Toggle output register of pin on event

Bits 4:0 – PID0[4:0] PORT Event Pin Identifier 0

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