There are up to four input event pins for each PORT group. Each byte of
this register addresses one Event input pin.
Table 33-17. Register Bit Attribute
Legend
Symbol
Description
Symbol
Description
Symbol
Description
R
Readable bit
HC
Cleared by Hardware
(Grey cell)
Unimplemented
W
Writable bit
HS
Set by Hardware
X
Bit is unknown at Reset
K
Write to clear
S
Software settable bit
—
—
Name:
CTRL
Offset:
0x24
Reset:
0x00000000
Property:
RW
Bit
31
30
29
28
27
26
25
24
SAMPLING[31:24]
Access
W
W
W
W
W
W
W
W
Reset
0
0
0
0
0
0
0
0
Bit
23
22
21
20
19
18
17
16
SAMPLING[23:16]
Access
W
W
W
W
W
W
W
W
Reset
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
SAMPLING[15:8]
Access
W
W
W
W
W
W
W
W
Reset
0
0
0
0
0
0
0
0
Bit
7
6
5
4
3
2
1
0
SAMPLING[7:0]
Access
W
W
W
W
W
W
W
W
Reset
0
0
0
0
0
0
0
0
Bits 31:0 – SAMPLING[31:0] Input Sampling Mode
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