36.3 Endpoint Bank, Packet Size

Table 36-26. Register Bit Attribute Legend
Symbol	Description	Symbol	Description	Symbol	Description
R	Readable bit	HC	Cleared by Hardware	(Grey cell)	Unimplemented
W	Writable bit	HS	Set by Hardware	X	Bit is unknown at Reset
K	Write to clear	S	Software settable bit	—	—

Name:	PCKSIZE - DEVICE_DESC_BANK Mode
Offset:	0x004
Property:	RW


Bit	31	30	29	28	27	26	25	24
	AUTO_ZLP	SIZE[2:0]			MULTI_PACKET_SIZE[13:10]
Access	RW	RW	RW	RW	RW	RW	RW	RW
Reset


Bit	23	22	21	20	19	18	17	16
	MULTI_PACKET_SIZE[9:2]
Access	RW	RW	RW	RW	RW	RW	RW	RW
Reset


Bit	15	14	13	12	11	10	9	8
	MULTI_PACKET_SIZE[1:0]		BYTE_COUNT[13:8]
Access	RW	RW	RW	RW	RW	RW	RW	RW
Reset


Bit	7	6	5	4	3	2	1	0
	BYTE_COUNT[7:0]
Access	RW	RW	RW	RW	RW	RW	RW	RW
Reset

Bit 31 – AUTO_ZLP Automatic Zero Length Packet

Bits 30:28 – SIZE[2:0] Enpoint size

Bits 27:14 – MULTI_PACKET_SIZE[13:0] Multi Packet In or Out size

Bits 13:0 – BYTE_COUNT[13:0] Byte Count

The online versions of the documents are provided as a courtesy. Verify all content and data in the device’s PDF documentation found on the device product page.