36.10 Host Bank, Host Status Pipe
| Symbol | Description | Symbol | Description | Symbol | Description |
|---|---|---|---|---|---|
| R | Readable bit | HC | Cleared by Hardware | (Grey cell) | Unimplemented |
| W | Writable bit | HS | Set by Hardware | X | Bit is unknown at Reset |
| K | Write to clear | S | Software settable bit | — | — |
| Name: | STATUS_PIPE - HOST_DESC_BANK Mode |
| Offset: | 0x00E |
| Property: | RW |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| Access | |||||||||
| Reset |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| ERCNT[2:0] | CRC16ER | TOUTER | PIDER | DAPIDER | DTGLER | ||||
| Access | RW | RW | RW | RW | RW | RW | RW | RW | |
| Reset | |||||||||