36.9 Host Bank, Host Control Pipe

Table 36-32. Register Bit Attribute Legend
Symbol	Description	Symbol	Description	Symbol	Description
R	Readable bit	HC	Cleared by Hardware	(Grey cell)	Unimplemented
W	Writable bit	HS	Set by Hardware	X	Bit is unknown at Reset
K	Write to clear	S	Software settable bit	—	—

Name:	CTRL_PIPE - HOST_DESC_BANK Mode
Offset:	0x00C
Reset:	0x0000
Property:	RW


Bit	15	14	13	12	11	10	9	8
	PERMAX[3:0]				PEPNUM[3:0]
Access	RW	RW	RW	RW	RW	RW	RW	RW
Reset	0	0	0	0	0	0	0	0


Bit	7	6	5	4	3	2	1	0
		PDADDR[6:0]
Access		RW	RW	RW	RW	RW	RW	RW
Reset		0	0	0	0	0	0	0

Bits 15:12 – PERMAX[3:0] Pipe Error Max Number

Bits 11:8 – PEPNUM[3:0] Pipe Endpoint Number

Bits 6:0 – PDADDR[6:0] Pipe Device Adress

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