37.8.43 Tx Buffer Configuration
| Symbol | Description | Symbol | Description | Symbol | Description |
|---|---|---|---|---|---|
| R | Readable bit | HC | Cleared by Hardware | (Grey cell) | Unimplemented |
| W | Writable bit | HS | Set by Hardware | X | Bit is unknown at Reset |
| K | Write to clear | S | Software settable bit | — | — |
This register is write-restricted and only writable if bit fields CCCR.CCE = 1 and CCCR.INIT = 1.
Note: Be aware that the sum of TFQS and
NDTB may not be greater than 32. There is no check for erroneous configurations. The
Tx Buffers section in the Message RAM starts with the dedicated Tx Buffers.
| Name: | TXBC |
| Offset: | 0x1C0 |
| Reset: | 0x00000000 |
| Property: | Write-restricted |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| TFQM | TFQS[5:0] | ||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | ||
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | ||
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| NDTB[5:0] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | |||
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | |||
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| TBSA[15:8] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| TBSA[7:0] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
Bit 30 – TFQM Tx FIFO/Queue Mode
| Value | Description |
|---|---|
| 0 | Tx FIFO operation. |
| 1 | Tx Queue operation. |
Bits 29:24 – TFQS[5:0] Transmit FIFO/Queue Size
| Value | Description |
|---|---|
| 0 | No Tx FIFO/Queue. |
| 1 - 32 | Number of Tx Buffers used for Tx FIFO/Queue. |
| >32 | Values greater than 32 are interpreted as 32. |
Bits 21:16 – NDTB[5:0] Number of Dedicated Transmit Buffers
| Value | Description |
|---|---|
| 0 | No Tx FIFO/Queue. |
| 1 - 32 | Number of Tx Buffers used for Tx FIFO/Queue. |
| >32 | Values greater than 32 are interpreted as 32. |