37.8.25 Interrupt Enable

Table 37-33. Register Bit Attribute Legend
SymbolDescriptionSymbolDescriptionSymbolDescription
RReadable bitHCCleared by Hardware(Grey cell)Unimplemented
WWritable bitHSSet by HardwareXBit is unknown at Reset
KWrite to clearSSoftware settable bit
Name: IE
Offset: 0x154
Reset: 0x00000000
Property: RW

Bit 3130292827262524 
   ARAEPEDEPEAEWDIEBOEEWE 
Access R/WR/WR/WR/WR/WR/W 
Reset 000000 
Bit 2322212019181716 
 EPEELOEBEUEBECEDRXETOOEMRAFETSWE 
Access R/WR/WR/WR/WR/WR/WR/WR/W 
Reset 00000000 
Bit 15141312111098 
 TEFLETEFFETEFWETEFNETFEETCFETCEHPME 
Access R/WR/WR/WR/WR/WR/WR/WR/W 
Reset 00000000 
Bit 76543210 
 RF1LERF1FERF1WERF1NERF0LERF0FERF0WERF0NE 
Access R/WR/WR/WR/WR/WR/WR/WR/W 
Reset 00000000 

Bit 29 – ARAE Access to Reserved Address Enable

ValueDescription
0Interrupt disabled.
1Interrupt enabled.

Bit 28 – PEDE Protocol Error in Data Phase Enable

ValueDescription
0Interrupt disabled.
1Interrupt enabled.

Bit 27 – PEAE Protocol Error in Arbitration Phase Enable

ValueDescription
0Interrupt disabled.
1Interrupt enabled.

Bit 26 – WDIE Watchdog Interrupt Interrupt Enable

ValueDescription
0Interrupt disabled.
1Interrupt enabled.

Bit 25 – BOE Bus_Off Status Interrupt Enable

ValueDescription
0Interrupt disabled.
1Interrupt enabled.

Bit 24 – EWE Warning Status Interrupt Enable

ValueDescription
0Interrupt disabled.
1Interrupt enabled.

Bit 23 – EPE Error Passive Interrupt Enable

ValueDescription
0Interrupt disabled.
1Interrupt enabled.

Bit 22 – ELOE Error Logging Overflow Interrupt Enable

ValueDescription
0Interrupt disabled.
1Interrupt enabled.

Bit 21 – BEUE Bit Error Uncorrected Interrupt Enable

ValueDescription
0Interrupt disabled.
1Interrupt enabled.

Bit 20 – BECE Bit Error Corrected Interrupt Enable

ValueDescription
0Interrupt disabled.
1Interrupt enabled.

Bit 19 – DRXE Message Stored to Dedicated Rx Buffer Interrupt Enable

ValueDescription
0Interrupt disabled.
1Interrupt enabled.

Bit 18 – TOOE Timeout Occurred Interrupt Enable

ValueDescription
0Interrupt disabled.
1Interrupt enabled.

Bit 17 – MRAFE Message RAM Access Failure Interrupt Enable

ValueDescription
0Interrupt disabled.
1Interrupt enabled.

Bit 16 – TSWE Timestamp Wraparound Interrupt Enable

ValueDescription
0Interrupt disabled.
1Interrupt enabled.

Bit 15 – TEFLE Tx Event FIFO Element Lost Interrupt Enable

ValueDescription
0Interrupt disabled.
1Interrupt enabled.

Bit 14 – TEFFE Tx Event FIFO Full Interrupt Enable

ValueDescription
0Interrupt disabled.
1Interrupt enabled.

Bit 13 – TEFWE Tx Event FIFO Watermark Reached Interrupt Enable

ValueDescription
0Interrupt disabled.
1Interrupt enabled.

Bit 12 – TEFNE Tx Event FIFO New Entry Interrupt Enable

ValueDescription
0Interrupt disabled.
1Interrupt enabled.

Bit 11 – TFEE Tx FIFO Empty Interrupt Enable

ValueDescription
0Interrupt disabled.
1Interrupt enabled.

Bit 10 – TCFE Transmission Cancellation Finished Interrupt Enable

ValueDescription
0Interrupt disabled.
1Interrupt enabled.

Bit 9 – TCE Timestamp Completed Interrupt Enable

ValueDescription
0Interrupt disabled.
1Interrupt enabled.

Bit 8 – HPME High Priority Message Interrupt Enable

ValueDescription
0Interrupt disabled.
1Interrupt enabled.

Bit 7 – RF1LE Rx FIFO 1 Message Lost Interrupt Enable

ValueDescription
0Interrupt disabled.
1Interrupt enabled.

Bit 6 – RF1FE Rx FIFO 1 FIFO Full Interrupt Enable

ValueDescription
0Interrupt disabled.
1Interrupt enabled.

Bit 5 – RF1WE Rx FIFO 1 Watermark Reached Interrupt Enable

ValueDescription
0Interrupt disabled.
1Interrupt enabled.

Bit 4 – RF1NE Rx FIFO 1 New Message Interrupt Enable

ValueDescription
0Interrupt disabled.
1Interrupt enabled.

Bit 3 – RF0LE Rx FIFO 0 Message Lost Interrupt Enable

ValueDescription
0Interrupt disabled.
1Interrupt enabled.

Bit 2 – RF0FE Rx FIFO 0 Full Interrupt Enable

ValueDescription
0Interrupt disabled.
1Interrupt enabled.

Bit 1 – RF0WE Rx FIFO 0 Watermark Reached Interrupt Enable

ValueDescription
0Interrupt disabled.
1Interrupt enabled.

Bit 0 – RF0NE Rx FIFO 0 New Message Interrupt Enable

ValueDescription
0Interrupt disabled.
1Interrupt enabled.