37.8.3 Interrupt Enable Clear Register
| Symbol | Description | Symbol | Description | Symbol | Description |
|---|---|---|---|---|---|
| R | Readable bit | HC | Cleared by Hardware | (Grey cell) | Unimplemented |
| W | Writable bit | HS | Set by Hardware | X | Bit is unknown at Reset |
| K | Write to clear | S | Software settable bit | — | — |
| Name: | INTENCLR |
| Offset: | 0x028 |
| Reset: | 0x00000000 |
| Property: | R/K |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| Access | |||||||||
| Reset |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| Access | |||||||||
| Reset |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| BERR | DBG | ||||||||
| Access | R/K | R/K | |||||||
| Reset | 0 | 0 |
Bit 1 – BERR Bus Error Interrupt Enable
Writing '0' to this bit has no effect.
Writing '1' to this bit will clear the Bus Error Interrupt Enable bit, which disables the Bus Error interrupt.
Bit 0 – DBG Debug Message Interrupt Disable
Writing '0' to this bit has no effect.
Writing a '1' to this bit will clear the Debug Message Interrupt Enable bit, which disables the Debug Message Interrupt.