21.5.5.1.1 PLL Initialization, Enabling, and Disabling

The PLL is enabled by writing a ‘1’ to the Enable bit in the Control register (PLLCTRL.ENABLE). The PLL is disabled by writing a ‘0’ to PLLCTRL.ENABLE.

Note: If the PLL is active, the user must ensure that at no time do they violate the minimum or maximum frequency ranges specified for FPFD, FVCO, and FCLK_PLL. Failure to do so destabilize the VCO and lead to unpredictable behavior. Therefore carefully select the order in which the user configures the various scaler values in the PLL, based on the FCKR clock source frequencies used in the application.