21.5.5.1.5 PLL Disabling

The PLL is disabled by writing a ‘0’ to PLLCTRL.ENABLE. Due to the synchronization of control and configuration registers, generation of internal timings to stop and power-down properly, the PLL will be active for a few microseconds after CTRLA.ENABLE is cleared. The end of the PLL activity can be checked with the Status Lock bit (STATUS.LOCK) being ‘0’. The PLL reference must not be stopped until the STATUS.LOCK is read ‘0’.